Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

Devanathan, V. R.; Ravikumar, C.P.; Kamakoti, V.

doi:10.1109/vts.2007.34

Cited by 37 publications

(22 citation statements)

References 16 publications

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“…This improves the effectiveness of capture power reduction, since more X-bits can be made available for capture-risky vectors. On the other hand, while low-capture-power ATPG [7] is helpful for reducing capture power, its run time is long and the test vector count is large if it must be performed for a large number of faults. Fortunately, in the flow of Fig.…”

Section: Importance Of Capture-safety Checkingmentioning

confidence: 99%

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A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Miyase

Sakai

Wen

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYTest power has become a critical issue, especially for lowpower devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capturesafety checking mandatory for test vectors. However, previous capturesafety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-TimeRelation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capturesafety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

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Section: Importance Of Capture-safety Checkingmentioning

confidence: 99%

“…That is, unexpected test responses may be captured in C 2 , even though the circuit-under-test is defect-free and functionally operational. Particularly in the testing of high-speed devices, even a small increase in delay due to excessive IR-drop may cause capture malfunction, resulting in test-induced yield loss [7].…”

Section: Introductionmentioning

confidence: 99%

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Miyase

Sakai

Wen

et al. 2013

IEICE Trans. Inf. & Syst.

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“…A popular scheme is to use the fanout count plus one [8] as the standard cell's weight. Unit weight assignment [4], i.e., the toggle count, and load capacitance [2] 978-1-4244-5766-3/10/$26.00 ©2010 IEEE 6B-1 are also often employed. To speed up computation, some approaches assign zero weight to all but the flip-flop.…”

Section: Weight Assignmentmentioning

confidence: 99%

“…The techniques in [18,4] utilize timed logic simulation to obtain the temporal distribution of switching events. A launch cycle is divided into several equal-length time slices; then, the instantaneous WSA of each time slice is computed.…”

Section: Temporal Distributionmentioning

confidence: 99%

Improved weight assignment for logic switching activity during at-speed test pattern generation

Pan

Wang

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.

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“…The former includes the partial capture scheme [19]; the latter includes the ATPG-based techniques in [6,18,20,22,8,14,1] and the post-ATPG Xfilling techniques in [3,21,15,24]. …”

Section: Power Supply Noise Induced Yield Lossmentioning

confidence: 99%

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

Lin¹,

Wu²,

Huang³

2008

2008 17th Asian Test Symposium

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This paper presents PHS-Fill, an ATPG technique that reduces (1) power supply noise for scan-based at-speed testing, and (2) test data volume in a Huffman coding based test compression environment. PHS-Fill first identifies the preferred Huffman symbols; these symbols correspond to the test pattern templates that improve test compression and reduces power supply noise at the same time. ATPG then biases its primary input assignments so that the test pattern blocks match the preferred symbols whenever possible. Simulation results on ISCAS89 and ITC99 benchmark circuits show that PHS-Fill is a promising solution.

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Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

Cited by 37 publications

References 16 publications

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Improved weight assignment for logic switching activity during at-speed test pattern generation

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

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