Giving Text Analytics a Boost

Polig, Raphael; Atasu, Kubilay; Chiticariu, Laura; Hagleitner, Christoph; Hofstee, H. Peter; Reiss, Frederick; Zhu, Huaiyu; Sitaridi, Eva

doi:10.1109/mm.2014.69

Cited by 15 publications

(7 citation statements)

References 24 publications

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“…Specifically, a FW thread is only responsible for configuring the HW by writing to memory mapped registers, or polling the interrupt status register for data transmission, or receiving incoming data packets. Furthermore, we observe producerconsumer interaction patterns in many practical industrial co-designs from IBM [8,18,19], RockBox Media Player [1], and others codesigns. In this paper, we verify co-designs that exhibit producerconsumer interaction behavior.…”

Section: Proposed Methodologymentioning

confidence: 95%

“…We have shown that this is extremely beneficial for co-designs that exhibits producer-consumer relationship. Such interaction pattern is prevalent in many practical co-designs [1,8,18,19]. However, the proposed verification approach is not applicable for co-designs that exhibits true concurrency [5], that is, when a SW and its interacting HW threads do not exhibit producer-consumer relationship.…”

Section: Limitations Of Proposed Approachmentioning

confidence: 99%

“…A scalable HW/SW co-verification tool need only check those parts of the co-verification model that pertain to the given co-specification model. Second, the SW in a typical HW/SW co-design only exercises a fragment of the HW state-space [8,18,19]. Formal tools may use this fact to verify only the HW functionality exercised by the SW, ignoring or abstracting the rest.…”

Section: Introductionmentioning

confidence: 99%

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Hardware/Software Co-verification Using Path-based Symbolic Execution

Mukherjee¹,

Joshi²,

O’Leary³

et al. 2020

Preprint

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Conventional tools for formal hardware/software co-verification use bounded model checking techniques to construct a single monolithic propositional formula. Formulas generated in this way are extremely complex and contain a great deal of irrelevant logic, hence are difficult to solve even by the state-of-the-art Satisfiability (SAT) solvers. In a typical hardware/software co-design the firmware only exercises a fraction of the hardware state-space, and we can use this observation to generate simpler and more concise formulas. In this paper, we present a novel verification algorithm for hardware/software co-designs that identify partitions of the firmware and the hardware logic pertaining to the feasible execution paths by means of path-based symbolic simulation with custom path-pruning, propertyguided slicing and incremental SAT solving. We have implemented this approach in our tool COVERIF. We have experimentally compared COVERIF with HW-CBMC, a monolithic BMC based co-verification tool, and observed an average speed-up of 5× over HW-CBMC for proving safety properties as well as detecting critical co-design bugs in an open-source Universal Asynchronous Receiver Transmitter design and a large SoC design.

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Section: Proposed Methodologymentioning

confidence: 95%

Section: Limitations Of Proposed Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hardware/Software Co-verification Using Path-based Symbolic Execution

Mukherjee¹,

Joshi²,

O’Leary³

et al. 2020

Preprint

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“…We report an industrial application of HW-CBMC on the Text Analytics FPGA Accelerator (TAA) co-design [14,13]. Text analytics is key in big data analytics.…”

Section: Introductionmentioning

confidence: 99%

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Mukherjee

Purandare

Polig

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

Self Cite

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Verification is indispensable for building reliable of hardware/software co-designs. However, the scope of formal methods in this domain is limited. This is attributed to the lack of unified property specification languages, the semantic gap between hardware and software components, and the lack of verifiers that support both C and Verilog/VHDL. To address these limitations, we present an approach that uses a bounded co-verification tool, HW-CBMC, for formally validating hardware/software co-designs written in Verilog and C. Properties are expressed in C enriched with specialpurpose primitives that capture temporal correlation between hardware and software events. We present an industrial case-study, proving bounded safety properties as well as discovering critical codesign bugs on a large and complex text analytics FPGA accelerator from IBM R .

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“…These raw data typically consist of irregular data types, and are poorly suited for traditional processor register types. In contrast to the initial stages or leaf processing steps, once the data has been filtered and formed into structured data, parallelism is greatly reduced [7].…”

Section: Introductionmentioning

confidence: 99%

CAPI: A Coherent Accelerator Processor Interface

Stuecheli¹,

Blaner²,

Johns³

et al. 2015

IBM J. Res. & Dev.

148

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Heterogeneous computing systems combine different types of compute elements that share memory. A specific class of heterogeneous systems discussed in this paper pairs traditional general-purpose processing cores and accelerator units. While this arrangement enables significant gains in application performance, device driver overheads and operating system code path overheads can become prohibitive. The I/O interface of a processor chip is a well-suited attachment point from a system design perspective, in that standard server models can be augmented with application-specific accelerators. However, traditional I/O attachment protocols introduce significant device driver and operating system software latencies. With the Coherent Accelerator Processor Interface (CAPI), we enable attaching an accelerator as a coherent CPU peer over the I/O physical interface. The CPU peer features consist of a homogeneous virtual address space across the CPU and accelerator, and hardware-managed caching of this shared data on the I/O device. This attachment method greatly increases the opportunities for acceleration due to the much shorter software path length required to enable its use compared to a traditional I/O model.

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Giving Text Analytics a Boost

Cited by 15 publications

References 24 publications

Hardware/Software Co-verification Using Path-based Symbolic Execution

Hardware/Software Co-verification Using Path-based Symbolic Execution

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

CAPI: A Coherent Accelerator Processor Interface

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