Germanium Quantum-Dot Single-Hole Transistors with Self-organized Tunnel Barriers and Self-aligned Electrodes Using Ingenious Sidewall Spacer and Oxidation Techniques

Pan, Rong-Cun; Wang, I-Hsiang; Lai, Chi-Cheng; George, T.; Lin, Horng–Chih; Li, Peiwen

doi:10.1109/edtm53872.2022.9798091

Cited by 1 publication

(3 citation statements)

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“…2 shows that for a given process time of 40 min for thermal oxidation, an increase in the included angle (from 30 o to 90 o ) of Trench I through layout design and nanofabrication results in the enhanced penetration of Si 3 N 4 spacer layers by the Ge QD, further reducing the tunnel-barrier width between the Ge QD and Si electrodes. [14] 3 > JEDS-2022-07-0194-R < Fig. 2.…”

Section: B Controllable Ge Qd Penetration Into the Si 3 N 4 Layermentioning

confidence: 99%

“…1. [14] Starting with an SOI substrate with a 50 nm-thick, boron-doped Si (100) layer, a triangle-shaped Si trench (denoted as Trench I) was produced using electron-beam lithography (EBL) and SF6/C4F8 plasma etching (Fig. 1a).…”

Section: Experimental Fabrication Of Ge Qds Shtsmentioning

confidence: 99%

“…2). [14] The Ge QD is formed in a self-assembled approach via Ge interstitial condensation, Ostwald ripening, and the ultimate complete coalescence of Ge nanocrystallites generated from the original poly-Si0.85Ge0.15 island during the selective oxidation process. [9] A significant fabrication advantage of our approach is the size tunability of the Ge QDs that is essentially determined by the total Ge content of the poly-Si1-xGex spacer island [9][10][11][12].…”

Section: A Precision Fabrication Of Self-assembled Ge-qd At the Desig...mentioning

confidence: 99%

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Germanium Spherical Quantum-Dot Single-Hole Transistors With Self-Organized Tunnel Barriers and Self-Aligned Electrodes

Lai

Pan

Wang

et al. 2023

IEEE J. Electron Devices Soc.

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We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers of Si3N4. A combination of lithographic patterning, sidewall spacers, and selfassembled growth was used for fabrication. The core experimental approach is based on the selective oxidation of poly-SiGe spacer islands located at the specially designed included-angle locations of Si3N4/Si-trenches. By adjusting processing times for conformal deposition, etch back and thermal oxidation, good tunability in the Ge QD size and its tunnel-barrier widths were controllably achieved. Each Ge QD is electrically addressable via self-aligned Si gate and reservoirs, thus offering an effective building block for implementing single-charge devices.

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Section: B Controllable Ge Qd Penetration Into the Si 3 N 4 Layermentioning

confidence: 99%

Section: Experimental Fabrication Of Ge Qds Shtsmentioning

confidence: 99%