GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools

Mahzoon, Alireza; Große, Daniel; Drechsler, Rolf

doi:10.1007/978-3-030-68071-8_9

Cited by 13 publications

(5 citation statements)

References 19 publications

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“…In our last rewriting technique "Common-Rewriting" we identify nodes in the AIG that only have one parent node and eliminate them. However, all our techniques are highly tailored to the selected benchmarks, generated by Boolector (btor) [83], AOKI [53], and GenMul [81]. The covered rewriting patterns, except for half-adders, can be seen in Fig.…”

Section: Variable Eliminationmentioning

confidence: 99%

“…We repeat the experiment using "sp-ar-rc"-multipliers with input bit-widths n in the interval [4,128], which are generated using the tool GenMul [81]. These multipliers can be seen on the right side of Fig.…”

Section: Simple Multipliersmentioning

confidence: 99%

“…We only have access to truncated multipliers using SMT models, which we generated with Boolector [83]. Additionally we generated benchmarks of large multipliers with Gen-Mul [81] (which only scales up to 512 bits), Boolector [83] and generator scripts by Arist Kojevnikov [52]. The multiplier architectures of [52,83] are very simple architectures without any optimizations.…”

Section: C7 Experimentsmentioning

confidence: 99%

“…A size of 0 means, that the final stage adder is not a Benchmarks are either generated by the Arithmetic Module Generator of [53] or by Boolector [83] (btor). PPG: simple (sp), Booth (bp) PPA: Dadda tree (dt), Wallace tree (wt), balanced delay tree (bd), array (ar), compressor tree (ct), overturned-stairs tree (os) FSA: Ladner-Fischer (lf), carry look-ahead (cl), Kogge-Stone (ks), carry-skip (ck), ripple-carry (rc), Brent-Kung (bk), conditional sum (cu), carry select (cs) Benchmarks generated by Boolector [83] (btor), from [52] (kjvnkv) and [81]. PPG: simple (sp) PPA: array (ar), Dadda tree (dt), Wallace tree (wt) FSA: ripple-carry (rc), Ladner-Fischer (lf), Brent-Kung (bk)…”

Section: C7 Experimentsmentioning

confidence: 99%

“…For the experiments of Table F.1 we generated PAC proofs as in previous work [62,63] in order to validate the correctness of multiplier circuits. The multipliers are either generated with the AMG [53], BOOLECTOR [83] or GENMUL [81].…”

Section: F5 Evaluationmentioning

confidence: 99%

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Formal verification of multiplier circuits using computer algebra

Kaufmann

2022

It - Information Technology

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Digital circuits are widely utilized in computers, because they provide models for various digital components and arithmetic operations. Arithmetic circuits are a subclass of digital circuits that are used to execute Boolean algebra. To avoid problems like the infamous Pentium FDIV bug, it is critical to ensure that arithmetic circuits are correct. Formal verification can be used to determine the correctness of a circuit with respect to a certain specification. However, arithmetic circuits, particularly integer multipliers, represent a challenge to current verification methodologies and, in reality, still necessitate a significant amount of manual labor. In my dissertation we examine and develop automated reasoning approaches based on computer algebra, where the word-level specification, modeled as a polynomial, is reduced by a Gröbner basis inferred by the gate-level representation of the circuit. We provide a precise formalization of this reasoning process, which includes soundness and completeness arguments and adds to the mathematical background in this field. On the practical side we present an unique incremental column-wise verification algorithm and preprocessing approaches based on variable elimination that simplify the inferred Gröbner basis. Furthermore, we provide an algebraic proof calculus in this thesis that allows obtaining certificates as a by-product of circuit verification in order to boost confidence in the outcomes of automated reasoning tools. These certificates can be efficiently verified with independent proof checking tools.

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Section: Variable Eliminationmentioning

confidence: 99%

Section: Simple Multipliersmentioning

confidence: 99%

Section: C7 Experimentsmentioning

confidence: 99%

Section: C7 Experimentsmentioning

confidence: 99%