Generic Self Repair Architecture with Multiple Fault Handling Capability

Baláž, Marcel; Kristofik, Stefan

doi:10.1109/dsd.2015.118

Cited by 5 publications

(15 citation statements)

References 10 publications

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“…adders, ALUs) due to the reduction in the switching circuitry area. However, when the area of reconfiguration logic is assumed as well, the impact of the size of FBs on the overall area can be reduced [5].…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…In most cases, the area including reconfiguration logic can be kept well under the TMR area and both transient and permanent faults can be repaired [5].…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…Testing can take place during the startup period [4] or during the lifetime of a core. During the lifetime, it can take place either on-line during the normal operation mode of the core [5], or off-line during the core idle time [4], or the combination of on-line and off-line testing can be used [5].…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…A tester can be implemented locally within RLB [3] or externally to RLB [5]. Testing can take place during the startup period [4] or during the lifetime of a core.…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…The most feasible numbers of FBs per RLB were determined to be 1, 2 or 3, and the number of BBs per RLB to be 1 [5]. The resulting RLB architectures are thereby referred to as 1+1, 2+1 and 3+1.…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

See 4 more Smart Citations

Built-in self-repair architecture generator for digital cores

Kristofik

Baláž

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.

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Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…In most cases, the area including reconfiguration logic can be kept well under the TMR area and both transient and permanent faults can be repaired [5].…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

“…A tester can be implemented locally within RLB [3] or externally to RLB [5]. Testing can take place during the startup period [4] or during the lifetime of a core.…”

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

Section: A Basic Principles and Problems Of Logic Self Repairmentioning

confidence: 99%

See 3 more Smart Citations

Built-in self-repair architecture generator for digital cores

Kristofik

Baláž

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Error masking method based on the short-duration offline test

Belohoubek

Fišer

Schmidt

2017

Microprocessors and Microsystems

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Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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Generic Self Repair Architecture with Multiple Fault Handling Capability

Cited by 5 publications

References 10 publications

Built-in self-repair architecture generator for digital cores

Built-in self-repair architecture generator for digital cores

Error masking method based on the short-duration offline test

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

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