Generic Description and Synthesis of LDPC Decoders

Guilloud, Frédéric; Boutillon, Emmanuel; Tousch, Jacky; Danger, Jean‐Luc

doi:10.1109/tcomm.2007.908517

Cited by 45 publications

(24 citation statements)

References 16 publications

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“…1 (b). Since the sequential operation and flexibility between two updates, TPMP algorithm can be rearranged into many modified schedule [6]. To make a tradeoff between decoding performance and hardware complexity, a Modified Min-Sum (MSA) algorithm based on Rearranged Schedule TPMP algorithm (RS-TPMP) [31] is adopted to decode a zM b × zN b Block-LDPC codes and expressed as follows: 1) Initialization:…”

Section: Decoding Algorithmmentioning

confidence: 99%

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A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

Huang

Zeng

Chen

2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm 2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.

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Section: Decoding Algorithmmentioning

confidence: 99%

“…2) For i = 1 to i max iteration For j = 1 to M b , each check node c (6) End End 3) Check stop criterion after each iteration:…”

Section: Decoding Algorithmmentioning

confidence: 99%

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

Huang

Zeng

Chen

2012

IEICE Trans. Inf. & Syst.

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“…The well-known belief propagation (BP) [18] algorithm, originally formulated in the form of flooding or two-phase decoding [8], has been recently given way to the so-called layered or shuffled decoding [9,11,15]. The key point of layered decoding is the overlap of the traditional variable node (VN) and check node (CN) phase, so that each iteration is viewed as the concatenation of several layer elaborations or micro-iterations.…”

Section: Pipelined Layered Decodingmentioning

confidence: 99%

“…the two-phase decoding. In a semi-parallel CN-centric formulation [8], a layer spans W parity-check equations that are processed in parallel within a micro-iteration. Considering the set N (m) of the VNs connected to the CN m and W = 1, layered decoding computes:…”

Section: Pipelined Layered Decodingmentioning

confidence: 99%

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Gentile

Rovini

Fanucci

2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations

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“…It has also been shown that sequential updating doesn't increase the decoding complexity per iteration, thus allowing the convergence speed increase at no cost [10], [11]. Although the literature listed above presents a variety of sequential schedules, they have very similar performance results [10].…”

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confidence: 99%

LDPC Decoders with Informed Dynamic Scheduling

Casado¹,

Griot

Wesel

2010

IEEE Trans. Commun.

110

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Abstract-Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation (BP), or message-passing, algorithm over the factor graph of the code. The traditional message-passing scheduling, called flooding, consists of updating all the variable nodes in the graph, using the same pre-update information, followed by updating all the check nodes of the graph, again, using the same pre-update information. Recently, several studies show that sequential scheduling, in which messages are generated using the latest available information, significantly improves the convergence speed in terms of number of iterations. Sequential scheduling introduces the problem of finding the best sequence of message updates. We propose Informed Dynamic Scheduling (IDS) strategies that select the message-passing schedule according to the observed rate of change of the messages. In general, IDS strategies require computation to select the message to update but converge in fewer message updates because they focus on the part of the graph that has not converged. Moreover, IDS yields a lower errorrate performance than either flooding or sequential scheduling because IDS strategies overcome traditional trapping-set errors. This paper presents IDS strategies that address several issues including performance for short-blocklength codes, complexity, and implementability.

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Generic Description and Synthesis of LDPC Decoders

Cited by 45 publications

References 16 publications

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

LDPC Decoders with Informed Dynamic Scheduling

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