Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs

We present a method for construction of application-specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying the properties of the C code in terms of operation types, available parallelism, and other metrics. We then create an initial data path to exploit the available parallelism. We then apply designer-guided constraints to an interactive data path refinement algorithm that attempts to reduce the number of the most expensive components while meeting the constraints. Our experimental results show that our technique scales very well with the size of the C code. We demonstrate the efficiency of our technique on wide range of applications, from standard academic benchmarks to industrial size examples like the MP3 decoder. Each processor core was constructed and refined in under a minute, allowing the designer to explore several different configurations in much less time than needed for manual design. We compared our selection algorithm to the manual selection in terms of cost/performance and showed that our optimization technique achieves better cost/performance trade-off. We also synthesized our designs with programmable controller and, on average, the refined core have only 23% latency overhead, twice as many block RAMs and 36% fewer slices compared to the respective manual designs.

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“…(ii) RFOxI, where (O, I) ∈ {(2, 1), (4, 2), (6, 3), (8,4)} are the number of output and input ports.…”

Section: Results: Interactive Design Explorationmentioning

confidence: 99%

“…We used programmable controller unit, NISC compiler [2,3] to generate schedule and Verilog generator [7,8] for translating architecture description from ADL to Verilog. For synthesis and simulation of the designs, we used Xilinx ISE 8.1i and ModelSim SE 6.2 g running on a 3 GHz Intel Pentium 4 machine.…”

Section: Methodsmentioning

confidence: 99%

Automated Generation of Custom Processor Core from C Code

Trajković

Abdi

Nicolescu

et al. 2012

Journal of Electrical and Computer Engineering

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“…To design a custom processor dedicated to a specific application, the designer should specify first a datapath and a C code, which describes the target application. The formal ADL of the tool set, which is called generic netlist representation (GNR), captures the structural details of the datapath [20,21]. GNR describes the datapath as a netlist of components and assigns different attributes to each component.…”

Section: Typical Nisc Design Methodologymentioning

confidence: 99%

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

et al. 2016

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In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.

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“…and hardware environment (generation of HDL language). Another solution is to use the NISC (No-Instruction Set Computer) environment proposed by [28]. NISC is a new architecture and compiler technology for designing custom processors.…”

Section: Adlmentioning

confidence: 99%

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Damez

Sieler

Landrault

et al. 2011

J Real-Time Image Proc

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Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

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Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs

Cited by 7 publications

References 13 publications

Automated Generation of Custom Processor Core from C Code

Automated Generation of Custom Processor Core from C Code

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

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