Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs

Preuser, Thomas B.

doi:10.23919/fpl.2017.8056834

Cited by 16 publications

(24 citation statements)

References 14 publications

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“…Unlike parallel counters, GPCs allow input bits to have different weights, which, in the dot notation, make the GPCs appear as multi-column counters. Figure 2 shows the dot notation of some previously published GPCs [22]. Mathematically, GPCs are written as a tuple: (p n−1 , ..., p 1 , p 0 :q m−1 , ..., q 1 , q 0 ), where p i is the number of input bits in the i t h column, and q j is the number of output bits in the j th column.…”

Section: Generalized Parallel Countersmentioning

confidence: 99%

“…As their names suggest, the "shape" of a GPC can have a profound impact on its hardware implementation on FPGAs, and subsequently its performance and efficiency in a compressor tree. Popular metrics to quantify the efficiency of a GPC include [20,22]:…”

Section: Generalized Parallel Countersmentioning

confidence: 99%

“…Stage 0 in Figure 1b is a compressor tree that produces sum and carry bits as inputs into Stage 1, which are then evaluated by an RCA to produce the final result (see HA→FA→HA row in Figure 4b, which is the RCA stage). Compressor trees can be built using GPCs, compressors, or both, and efficient compressor tree design is an active area of research with large bodies of existing literature [11,12,[18][19][20][21][22]29].…”

Section: Adder and Compressor Treesmentioning

confidence: 99%

“…To quantify that claim, we analyzed optimal solutions of compressor trees from a set of 50+ micro-benchmarks that are commonly found in various domains (e.g. popcounting, multi-operand addition, FIR filters, etc) using efficient GPCs and compressors for Xilinx architecture from reference [22]. Figure 6 shows a histogram of the percentage count and cost (in LEs) for all GPCs across all solutions.…”

Section: Luxormentioning

confidence: 99%

“…To the best of our knowledge, this leads to the most efficient reported logic element based GPC, called C06060606, which can be mapped to just a single Xilinx slice. • A novel integer linear programming (ILP) formulation based on the flexible Ternary Adder approach proposed in [22] to optimally map compressor tree problems to LUXOR cells. • Quantitative investigation of the benefits of LUXOR and LUXOR+ architectures using a set of more than 50 microbenchmarks.…”

Section: Introductionmentioning

confidence: 99%

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Luxor

Rasoulinezhad

Siddhartha

Zhou

et al. 2020

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the first tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-specific modifications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modifications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of domains.BNN benchmarks benefit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-efficient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells.

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Section: Generalized Parallel Countersmentioning

confidence: 99%

Section: Generalized Parallel Countersmentioning

confidence: 99%

Section: Adder and Compressor Treesmentioning

confidence: 99%

Section: Luxormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Luxor

Rasoulinezhad

Siddhartha

Zhou

et al. 2020

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Sums of Weighted Bits

de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

Yuan

Huang

et al. 2019

IEEE Access

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Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel counters (GPCs) were synthesized on FPGAs to address this issue. Despite the improved timing performance of GPC-based compressor trees, area reduction is not as significant as delay, and can be further optimized. In this paper, we propose improved GPC mappings as well as new approaches for GPC cascading and binding for Xilinx FPGAs. With these improvements, we develop an integer linear programming (ILP) method for FPGA synthesis of GPC-based compressor trees that supports cascading and binding between GPCs. Experimental results show that the single-cycle compressor trees produced by the proposed ILP can reduce the average area by 42.40% compared with those generated by existing heuristic method, but are 13.16% slower; the pipelined compressor trees produced by the proposed ILP can reduce the average area by 33.43% at the cost of an average 14.35% decrease in maximum clock frequency compared with those obtained by existing heuristic method.INDEX TERMS Generalized parallel counter (GPC), compressor tree, integer linear programming (ILP), field programmable gate array (FPGA).

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Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs

Cited by 16 publications

References 14 publications

Luxor

Luxor

Sums of Weighted Bits

Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

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