Generating power-hungry test programs for power-aware validation of pipelined processors

Calimera, Andrea; Macii, Enrico; Ravotto, D.; Sánchez, Ernesto; Reorda, M. Sonza

doi:10.1145/1854153.1854171

Cited by 4 publications

(12 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this paper we propose an inexpensive technique 2 A decision-point is a point that a module's state (testing/heating/cooling) or test/heating node may change. (a) 22 to order the tests and heating sequences so that required temperature cycling effects can be achieved without the use of temperature chambers in a short time.…”

Section: Discussionmentioning

confidence: 99%

“…But, in order to have more effective heating sequences, input stimuli that generate even larger switching activities must be found. Authors in [22] have introduced an automated framework for finding high power test programs. The proposed approach is based on a meta-heuristic that generates alternative test programs and evaluates their power consumption.…”

Section: Temperature Cycling and Scheduling Techniquesmentioning

confidence: 99%

“…The proposed approach is based on a meta-heuristic that generates alternative test programs and evaluates their power consumption. The alternatives with promising power consumptions are then used to generate the next generation of the test program alternatives [22]. A similar approach may be used in order to generate high power heating sequences.…”

Section: Temperature Cycling and Scheduling Techniquesmentioning

confidence: 99%

See 2 more Smart Citations

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

2015

View full text Add to dashboard Cite

In a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduction. Consequently these early-life failures lead to products that fail shortly after the start of their use. Artificially-accelerated temperature cycling, before the manufacturing test, helps to detect such early-life failures that are otherwise undetectable. A test-ordering based temperaturecycling acceleration technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration methods. All these result in a reduction in the overall test costs. The proposed method is a test-ordering and schedule based solution that enforces the required temperature cycling effect and simultaneously performs the tests whenever appropriate. Experimental results demonstrate the efficiency of the proposed technique.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Temperature Cycling and Scheduling Techniquesmentioning

confidence: 99%

Section: Temperature Cycling and Scheduling Techniquesmentioning

confidence: 99%

See 1 more Smart Citation

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

2015

View full text Add to dashboard Cite

show abstract

“…Moreover, specialized techniques for this purpose can be developed. These methods are, in essence, similar to [9]. The authors in [9] introduced a power-hungry test stimulus generation technique.…”

Section: Temperature-gradient Based Burn-in a Preliminaries Andmentioning

confidence: 99%

“…These methods are, in essence, similar to [9]. The authors in [9] introduced a power-hungry test stimulus generation technique. The produced stimuli cause large switching activity which results in large power density and high temperature.…”

Section: Temperature-gradient Based Burn-in a Preliminaries Andmentioning

confidence: 99%

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

Aghaee

Peng

Eles

2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3D stacked ICs compared with 2D ICs because of the larger temperature gradients in 3D stacked ICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed methods.Index Terms-3D Stacked IC test, burn-in, temperature gradients, test scheduling I. INTRODUCTION arge temperature gradients (e. g., temperature difference between two adjacent cores) exacerbate various types of defects including early-life failures and delay faults. The capability to detect these temperature-gradient induced defects is crucial for many ICs. In particular, three dimensional ICs exhibit considerably larger temperature gradients compared with normal ICs (for example, three times is reported in [29]) and therefore temperature-gradient based test is necessary for them.A promising technology for fabricating 3D ICs is based on Through-Silicon Vias (TSV) used for inter-die connections [11], [13], [17], [27]. The ICs fabricated using TSVs are commonly referred to as 3D Stacked IC (3D-SIC) [17]. The important advantages of this technology include high inter-die interconnect densities and low inter-die interconnect wire lengths. This leads to higher operating frequencies at lower power consumptions. A. Test for Early-Life FailuresBurn-in is a common way of accelerating and detecting earlylife failures and it should be done with low cost in a reasonably short time. For this purpose, usually the dies are operated at elevated temperature and voltage. The elevated temperature and voltage speed up the aging and wear mechanisms so that the dies experience their early life before testing. The wear mechanisms that are speeded up include metal stress voiding and electromigration, metal slivers bridging shorts, as well as gate-oxide wear-out and breakdown [23].

show abstract

Peak Power Estimation: A Case Study on CPU Cores

Bernardi

Carvalho

Sánchez

et al. 2012

2012 IEEE 21st Asian Test Symposium

View full text Add to dashboard Cite

High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of overconsumption. Measuring power consumption is a very time consuming activity; therefore many works in the literature focused on the indirect ways to provide power consumption estimation in a fast manner. In this paper we concentrate on a similar issue, concentrating our effort on devising a fast method for the identification and estimation of the peak power produced by test patterns. In particular we provide a detailed discussion on case studies related to peak power estimation of CPU cores when executing functional patterns; the proposed method uses the gatelevel description of the CPU to identify a subset of time points over the entire test pattern that are showing the most significant peak power values. The proposed methodology has been validated on two case studies synthesized in a 65nm industrial technology.

show abstract

Generating power-hungry test programs for power-aware validation of pipelined processors

Cited by 4 publications

References 19 publications

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

Peak Power Estimation: A Case Study on CPU Cores

Contact Info

Product

Resources

About