Abstract-Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3D stacked ICs compared with 2D ICs because of the larger temperature gradients in 3D stacked ICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed methods.Index Terms-3D Stacked IC test, burn-in, temperature gradients, test scheduling I. INTRODUCTION arge temperature gradients (e. g., temperature difference between two adjacent cores) exacerbate various types of defects including early-life failures and delay faults. The capability to detect these temperature-gradient induced defects is crucial for many ICs. In particular, three dimensional ICs exhibit considerably larger temperature gradients compared with normal ICs (for example, three times is reported in [29]) and therefore temperature-gradient based test is necessary for them.A promising technology for fabricating 3D ICs is based on Through-Silicon Vias (TSV) used for inter-die connections [11], [13], [17], [27]. The ICs fabricated using TSVs are commonly referred to as 3D Stacked IC (3D-SIC) [17]. The important advantages of this technology include high inter-die interconnect densities and low inter-die interconnect wire lengths. This leads to higher operating frequencies at lower power consumptions.
A. Test for Early-Life FailuresBurn-in is a common way of accelerating and detecting earlylife failures and it should be done with low cost in a reasonably short time. For this purpose, usually the dies are operated at elevated temperature and voltage. The elevated temperature and voltage speed up the aging and wear mechanisms so that the dies experience their early life before testing. The wear mechanisms that are speeded up include metal stress voiding and electromigration, metal slivers bridging shorts, as well as gate-oxide wear-out and breakdown [23].