Generalized Symbolic Trajectory Evaluation — Abstraction in Action

Yang, Jin; Seger, Carl-Johan H.

doi:10.1007/3-540-36126-x_5

Cited by 40 publications

(65 citation statements)

References 16 publications

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“…Properties which are spread over infinite time intervals cannot be expressed in S T E , l e t a l o n e b e v e r i f i e d [ 5 , 6 ] . G S T E constitutes a very significant extension to STE [8][9][10]. It has been used successfully by INTEL on its new generation microprocessor designs.…”

Section: Generalized Symbolic Trajectory Evaluationsmentioning

confidence: 99%

Integration Verification in System on Chips Using Formal Techniques

Roy¹

2009

Micro Electronic and Mechanical Systems

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Section: Generalized Symbolic Trajectory Evaluationsmentioning

confidence: 99%

Integration Verification in System on Chips Using Formal Techniques

Roy¹

2009

Micro Electronic and Mechanical Systems

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“…GSTE is explained in several sources (e.g., [20,21,19], etc.). Here, we concentrate on the specification style used by GSTE and highlight its characteristics.…”

Section: Gste and Assertion Graphsmentioning

confidence: 99%

“…Existing GSTE theory provides an efficient procedure for model checking that a circuit obeys an assertion graph, as well as techniques based on abstract interpretation to combat state explosion [21]. What is missing, however, is all the supporting theory and algorithms that have developed around more established formalisms like CTL [5] or LTL [18].…”

Section: Introductionmentioning

confidence: 99%

Reasoning about GSTE Assertion Graphs

Casas²,

Yang³

2003

Lecture Notes in Computer Science

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Abstract. Generalized symbolic trajectory evaluation (GSTE) is a new modelchecking approach that combines the industrially-proven scalability and capacity of classical symbolic trajectory evaluation with the expressive power of temporallogic model checking. GSTE was originally developed at Intel and has been used successfully on Intel's next-generation microprocessors. However, the supporting theory and algorithms for GSTE are still immature. In particular, GSTE specifications are given as assertion graphs, a variety of ∀-automata, and although an efficient model-checking algorithm exists to verify whether a circuit model obeys a specification assertion graph, there is no work on reasoning about assertion graphs themselves. This paper presents new algorithms to leverage GSTE model checking to efficiently decide whether one assertion graph implies another, and to model check one assertion graph under the assumption that another is true (under regular GSTE acceptance conditions). These two operations -deciding whether one specification implies another and verifying under an assumption -are the fundamental building blocks of compositional verification and any higher-level reasoning about model-checking results, so the algorithms presented here are key steps to using GSTE in a broader verification framework. Preliminary experimental results applying our algorithms to real, industrial circuits and specifications show that our algorithms are useful in practice.

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“…We verify that if we write a value on a particular address, next time we read from it we obtain the same value, unless another write operation was performed in the meanwhile. Inspired by the work on GSTE of [20], we express the property by enumerating each address case so that the property automaton contains different subgraph for each case. The partitioned abstraction should take benefit from this, by keeping in each subgraph only the information regarding that particular memory address.…”

Section: Resultsmentioning

confidence: 99%

“…In [15,16], motivated by previous work on Generalized Symbolic Trajectory Evaluation (GSTE) [20], Property-Driven Partitioning (PDP) has been proposed as a new hybrid approach to LTL model checking. In this approach, the property automaton A is constructed explicitly, but its product with the system is represented in a partitioned fashion.…”

Section: Introductionmentioning

confidence: 99%

Property-Driven Partitioning for Abstraction Refinement

Sebastiani

Tonetta

Vardi³

Tools and Algorithms for the Construction and Analysis of Systems

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Abstract. Partitioning and abstraction have been studied extensively both in hardware and in software verification. The abstraction is typically partitioned according to the system design in the case of hardware or the control graph in the case of software. In this work we build on previous work on Property-Driven Partitioning (PDP), a hybrid Symbolic Model-Checking (SMC) technique for ω-regular properties in which the state space is partitioned according to the states of the property automaton. We investigate a new paradigm for abstraction refinement in SMC, which combines abstraction and PDP: each PDP partition may contain a different abstraction, so that it can be refined independently from the others; in case of a spurious counterexample π, the system is refined only in those partitions that are necessary to rule out π. We performed a preliminary experimental evaluation comparing standard Counterexample-Guided Abstraction Refinement (CEGAR) with its partitioned counterpart, which confirmed that the partitioned technique always allows for using coarser abstractions. While earlier work has shown that PDP almost always improves the performance of SMC, our experiments here show that this is not always the case for partitioned abstraction refinement, as in some cases the overhead due to the localization of the abstraction is too high.

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Generalized Symbolic Trajectory Evaluation — Abstraction in Action

Cited by 40 publications

References 16 publications

Integration Verification in System on Chips Using Formal Techniques

Integration Verification in System on Chips Using Formal Techniques

Reasoning about GSTE Assertion Graphs

Property-Driven Partitioning for Abstraction Refinement

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