Generalized fractional logistic map encryption system based on FPGA

Ismail, Sikiru Oluwarotimi; Said, Lobna A.; Rezk, Ahmed A.; Radwan, Ahmed G.; Madian, Ahmed H.; Abu-Elyazeed, Mohamed F.; Soliman, Ahmed M.

doi:10.1016/j.aeue.2017.05.047

Cited by 83 publications

(25 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Regarding to the DSP cells used, the proposed solution needs a higher quantity than others, as in [31] and [33]. However, it is also at the expense of reducing other parameters.…”

Section: Comparison With Other Solutionsmentioning

confidence: 99%

See 1 more Smart Citation

Chaotic Encryption for 10-Gb Ethernet Optical Links

Pérez-Resa

García-Bosque

Sánchez-Azqueta

et al. 2019

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper, a new physical layer encryption method for optical 10-Gb Ethernet links is proposed. Necessary modifications to introduce encryption in Ethernet 10GBase-R standard have been considered. This security enhancement has consisted of a symmetric streaming encryption of the 64b/66b data flow at physical coding sublayer level thanks to two keystream generators based on a chaotic algorithm. The overall system has been implemented and tested in a field programmable gate array. Ethernet traffic has been encrypted, transmitted, and decrypted over a multimode optical link. Experimental results are analyzed concluding that it is possible to cipher traffic at this level and hide the complete Ethernet traffic pattern from any passive eavesdropper. In addition, no overhead is introduced during encryption, getting no losses in the total throughput. Index Terms-Ethernet, 10GBASE-R, cryptography, stream cipher, skew tent map.

show abstract

“…Regarding to the DSP cells used, the proposed solution needs a higher quantity than others, as in [31] and [33]. However, it is also at the expense of reducing other parameters.…”

Section: Comparison With Other Solutionsmentioning

confidence: 99%

“…For example in both solutions Encryption_rate is lower than this work. Moreover, in [33] the complete state is taken as output and the key size is only 60 bits, which disminishes the security achieved by this solution.…”

Section: Comparison With Other Solutionsmentioning

confidence: 99%

Chaotic Encryption for 10-Gb Ethernet Optical Links

Pérez-Resa

García-Bosque

Sánchez-Azqueta

et al. 2019

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…In this work, we are interested in attacks related to the biometric model. FPGA circuits are preferred circuits for implementing cryptographic algorithms in relation to software implementations, in terms of security . The security of a cryptosystem is usually based on the secret key of the encryption key generator.…”

Section: Securing Fingerprint Biometric Templatesmentioning

confidence: 99%

An efficient and lightweight multi‐scroll chaos‐based hardware solution for protecting fingerprint biometric templates

Azzaz

Tanougast

Maali

et al. 2019

Int J Communication

View full text Add to dashboard Cite

This paper presents a new efficient and lightweight approach for enhancing the security of biometric models, namely, fingerprint templates, against possible attacks. The proposed design is based on Vernam stream cipher in which the key generator is designed in the hardware manner. The designed cryptosystem consists of using multi-scroll chaotic system that is characterized by a large key space and can be generated N × N grid multi-scroll attractors, with a good behavior of chaotic dynamic. The hardware approach is carried out through describing Euler method by VHDL. Field-programmable gate array (FPGA) experimental results validate the developed architecture while still providing a good compromise between hardware resources and performance. Indeed, security analysis also shows that the designed encryption algorithm is robust against statistical, brute force, and entropy attacks. Therefore, it can be considered as a lightweight security solution, which could be very useful in many embedded applications namely securing biometric authentication systems.

show abstract

“…Na comparação com outros trabalhos da literatura (Sreenath e Narayanan, 2018; Khani e Ahmadi, 2013), foi possível reduzir em 50% o número de elementos digitais por bit. Com essa redução, abre-se espaço para implementação em linguagem de descrição de hardware (VHDL, por exemplo) como já tem sido feito em outros trabalhos (Silva et al, 2017;Muthuswamy e Banerjee, 2015;Ismail et al, 2017). E apresentado também uma metodologia de perturbação de sistema muito simples, baseada na alteração do bit menos significativo do sistema, capaz de diminuir a degradação do caos.…”

Section: Introductionunclassified

Simplificação da representação digital do mapa tenda por meio de ponto fixo polarizado

Teixeira

Basilio

Nepomuceno

et al. 2019

Anais Do 14º Simpósio Brasileiro De Automação Inteligente

View full text Add to dashboard Cite

Chaotic systems have been investigated in several areas of engineering. In control theory, such systems have instigated the emergence of new techniques as well, have been used as a source of noise generation. The application of chaotic systems as pseudo-random numbers has also been widely employed in cryptography. One of the central aspects of these applications in high performance situations, such as those involving a large amount of data (Big Data), is the response of these systems in a short period of time. Despite the great advances in the design of chaotic systems in analog circuits, it is perceived less attention in the optimized design of these systems in the digital domain. In this work, the polarized fixed point representation is applied to reduce the number of digital elements. Using this approach, it was possible to significantly reduce the number of logic gates in the subtraction operation. When compared to other works in the literature, it has been viable to reduce by 50 % the number of elements per bit of the digital representation of the tent map. The chaoticity was evidenced with the calculation of the Lyapunov exponent. Histogram, entropy and autocorrelation tests were used satisfactorily to evaluate the randomness of the represented system. Resumo: Sistemas caóticos têm sido investigados em diversasáreas da engenharia. Na teoria de controle, tais sistemas têm instigado o surgimento de novas técnicas, bem como, têm sido utilizados como fonte de geração de ruído. A aplicação de sistemas caóticos como números pseudo-aleatórios também tem sido largamente empregada em criptografia. Um dos aspectos centrais nessas aplicações em situações que exigem alto desempenho, como as que envolvem um grande volume de dados (Big Data),é a resposta desses sistemas em um curto intervalo de tempo. Apesar de grandes avanços na concepção de sistemas caóticos em circuitos analógicos, percebese uma menor atenção no projeto otimizado desses sistemas no domínio digital. Neste trabalho, aplica-se a representação de ponto fixo polarizado para reduzir o número de componentes lógicos. Com tal emprego, foi possível reduzir significativamente o número de portas lógicas na operação de subtração. Quando comparado com outros trabalhos na literatura, foi possível reduzir em 50% o número de componentes por bit da representação digital do mapa tenda. A caoticidade foi evidenciada com o cálculo do expoente de Lyapunov. Histograma, entropia e teste de autocorrelação foram empregados satisfatoriamente para avaliar a aleatoriedade do sistema representado.

show abstract

Generalized fractional logistic map encryption system based on FPGA

Cited by 83 publications

References 20 publications

Chaotic Encryption for 10-Gb Ethernet Optical Links

Chaotic Encryption for 10-Gb Ethernet Optical Links

An efficient and lightweight multi‐scroll chaos‐based hardware solution for protecting fingerprint biometric templates

Simplificação da representação digital do mapa tenda por meio de ponto fixo polarizado

Contact Info

Product

Resources

About