In this paper we present Semi-bit-serial and programmable circuit architectures for performing arithmetic in GF(2") . The semi-bit-serial mathematical architectures offer a structure that operates faster than traditional bit-serial architectures, whilst offering considerably lower hardware requirements than a bit-parallel architecture. This new approach to arithmetic operations in G F (2m) is based on composite fjelds of the form G F ( (2")2) ( m = 2n) . It is also shown that these operators lend themselves to programmable architectures that operate in either GF(Zm) or GF(2") . The circuit architectures proposed in this paper support implementation in VLSI systems due to their regular and hardware efficient circuit structures and are therefore suited to use in ReedSolomon error-correction codecs.