General representation of CMOS structure transition time for timing library representation

Maurine, Philippe; Azémard, Nadine; Auvergne, D.

doi:10.1049/el:20020103

Cited by 4 publications

(25 citation statements)

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“…Indeed, as explicitly stated in these papers, models in [25,26] are not suitable for timing analysis of complex digital circuits. [12][13][14][15]: analysis and considerations…”

Section: Previously Proposed Modelsmentioning

confidence: 99%

“…The model in [12][13][14][15] overcomes the computational efficiency issues of the above-mentioned models, thanks to its intrinsic simplicity of the relationships involved. For this reason, it is analyzed in detail in this subsection.…”

Section: Model Inmentioning

confidence: 99%

“…Fundamentally, the model in [12][13][14][15] is based on a separate analysis of the output transition time under fast and slow inputs, as depicted in Figure 1 the output transition time OUT is well known to increase as depicted in Figure 1. Thus, OUT must be modeled with a different expression OUT,slow that increases as in increases, which is found to be proportional to √ in according to [12][13][14][15]. Unfortunately, this model is affected by a very low accuracy in nanometer technologies.…”

Section: Model Inmentioning

confidence: 99%

“…Until now, several papers addressing the analytical modeling of the output transition time have been published [12][13][14][15][16][17][18][19][20][21][22][23]. Most of these models are physically based, i.e.…”

Section: Introductionmentioning

confidence: 99%

“…As was suggested in [12][13][14][15] the proposed model is split into two analytical expressions that respectively hold for fast and slow inputs. The analytical expression under fast inputs is found from a transient circuit analysis and general considerations on the transition time dependencies.…”

Section: Introductionmentioning

confidence: 99%

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Simple and accurate modeling of the output transition time in nanometer CMOS gates

Alioto

Palumbo

Poli

2010

Circuit Theory & Apps

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In this paper, a model of the output transition time on nanometer CMOS gates is proposed. The development of this model follows the general approach used by Auvergne in (IEE Electron. Lett. separately models the output transition time under fast and slow inputs. The proposed model is based on a combined transient and DC circuit analysis, and requires a few simulations. This approach allows for strongly reducing the number of required parameters and simulations compared with other models proposed in the literature.The analytical model proposed is very simple and has a clear physical meaning, thereby allowing an efficient implementation in CAD tools performing timing analysis, as well as an easy scalability through different processes and technology generations. Spectre simulations on a 65 nm CMOS technology and the 45, 32, 22 nm Berkeley Predictive Technology Models (BPTM) [Berkeley Predictive Technology Model (BPTM). ONLINE@11/25/2008: http://www.eas.asu.edu/∼ptm/] show that the model accuracy is the same as the state-of-the-art models, with an average error of only 4%. Comparison with currently used table-based models showed also a significant reduction in the CPU time needed to simulate and characterize CMOS logic gates.

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“…Indeed, as explicitly stated in these papers, models in [25,26] are not suitable for timing analysis of complex digital circuits. [12][13][14][15]: analysis and considerations…”

Section: Previously Proposed Modelsmentioning

confidence: 99%