General Architecture for Hardware Implementation of Genetic Algorithm

Tachibana, Tatsuhiro; Murata, Yoshinori; Shibata, Naoki; Yasumoto, Keiichi; Ito, Minoru

doi:10.1109/fccm.2006.43

Cited by 23 publications

(16 citation statements)

References 1 publication

(3 reference statements)

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“…However, one of the main concerns in genetic algorithms is their convergence time that makes them inappropriate for real-time systems. To solve this problem, implementing genetic methods by hardware may be considered (Chen et al 2008;Tachibana et al 2006Tachibana et al , 2007Lei et al 2002). Also, in another algorithm presented by Ökdem and Karaboga (2006), ant colony (ACO) approach has been used to schedule disk requests.…”

Section: Related Workmentioning

confidence: 99%

“…To implement the proposed disk scheduling algorithm, we employed simple pipeline hardware architecture proposed in Chen et al (2008), Tachibana et al (2006), Lei et al (2002). To the best of our knowledge, no other researchers have provided a hardware module using sequential GA for real-time disk scheduling since now, however, the proposed method in Turton and Arsalan (1995) provides a hardware architecture of parallel GA for non-real time tasks, therefore, designing mentioned modules in an optimal way is the most novelty of this part.…”

Section: Novel Contributions Of This Articlementioning

confidence: 99%

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Hardware design of a new genetic based disk scheduling method

et al. 2010

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Disk management is an increasingly important aspect of operating systems research and development because it has great effect on system performance. As the gap between processor and disk performance continues to increase in modern systems, access to mass storage is a common bottleneck that ultimately limits overall system performance. In this paper, we propose hardware architecture of a new genetic based real-time disk scheduling method. Also, to have a precise simulation, a neural network is proposed to simulate seek-time of disks. Simulation results showed the hardware implementation of proposed algorithm outperformed software implementation in term of execution time, and other related works in terms of number of tasks that miss deadlines and average seeks.

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Section: Related Workmentioning

confidence: 99%

Section: Novel Contributions Of This Articlementioning

confidence: 99%

Hardware design of a new genetic based disk scheduling method

et al. 2010

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“…It contains programmable logic components and programmable interconnects [7]. FPGAs are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system [1] [8]. The FPGA contains CLB (Configurable Logic Blocks), Horizontal and Vertical lines.…”

Section: Introductionmentioning

confidence: 99%

VHDL Synthesis and Simulation of an Efficient Genetic Algorithm Based on FPGA

Rajeswaran

Madhu²,

Suryakalavathi

2013

Advances in Intelligent Systems and Computing

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Abstract. Genetic Algorithm (GA) is an artificial intelligence procedure and one of the probabilistic heuristic search algorithms based on the mechanism of natural selection and evaluation. The GA is used to select the characteristic parameters of the classifiers, the input features and find the optimum solution for a variety of complex problems like Very Large Scale Integrated (VLSI) design, layout and test automation. Field Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing and is very widely used in VLSI Circuits. The GA architecture is simulated and verified by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).

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“…With the requirements of realtime computing and low energy consumption, GAs were first adapted for FPGAs in 1995 [3]. In addition to a considerable number of conventional GA systems mentioned in [4], [5], [6], [20], FPGA-based master-slave GAs and dGAs have been demonstrated [7], [8], [9], [10], [11]. FPGA-based cGAs are also proposed in [12], [13], [14].…”

Section: Fpga-based Parallel Gamentioning

confidence: 99%

“…There have been previous attempts to adapt pGAs to FPGAs for acceleration or low power consumption [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. However, designing an FPGA-based pGA is not as easy as implementing multiple hardware blocks supporting a set of GA instances.…”

Section: Introductionmentioning

confidence: 99%

Automated framework for FPGA-based parallel genetic algorithms

Guo

Thomas

Guo

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Parallel genetic algorithms (pGAs) are a variant of genetic algorithms which can promise substantial gains in both efficiency of execution and quality of results. pGAs have attracted researchers to implement them in FPGAs, but the implementation always needs large human effort. To simplify the implementation process and make the hardware pGA designs accessible to potential non-expert users, this paper proposes a generalpurpose framework, which takes in a high-level description of the optimisation target and automatically generates pGA designs for FPGAs. Our pGA system exploits the two levels of parallelism found in GA instances and genetic operations, allowing users to tailor the architecture for resource constraints at compile-time. The framework also enables users to tune a subset of parameters at run-time without time-consuming recompilation. Our pGA design is more flexible than previous ones, and has an average speedup of 26 times compared to the multi-core counterparts over five combinatorial and numerical optimisation problems. When compared with a GPU, it also shows a 6.8 times speedup over a combinatorial application.

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General Architecture for Hardware Implementation of Genetic Algorithm

Cited by 23 publications

References 1 publication

Hardware design of a new genetic based disk scheduling method

Hardware design of a new genetic based disk scheduling method

VHDL Synthesis and Simulation of an Efficient Genetic Algorithm Based on FPGA

Automated framework for FPGA-based parallel genetic algorithms

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