gemV: A validated toolset for the early exploration of system reliability

Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability

“…exception of [7] that includes benchmarks described in MPI, reviewed approaches neither consider parallel programming libraries nor multicore processors on their experiments. Further, the majority of these works consider either simple inhouse (e.g., [4]) and bare metal applications (e.g., [8]) or small set of benchmarks (e.g., [5,6,9]), where only a specific ISA is considered. While the approaches presented by Hari et al [2,3] propose a hybrid simulation framework for SPARC core using Simics [10] and GEMS [11] simulators, remaining works rely on a single virtual platform simulator.…”

“…The increasing software and hardware complexity of such systems imposes exploration challenges, including: (ch1) conduct a large number of fault injection campaigns within a F. R. da Rosa reasonable time; (ch2) provide engineers with detailed observation of system's behavior in the presence of faults; and (ch3) identify relationships or associations between application profiling and specific platform parameters in large data sets resulting from the fault campaigns. Aiming to overcome the challenges ch1 and ch2, researchers are incorporating fault injection capabilities into virtual platform (VP) frameworks [2][3][4][5][6][7][8], enabling the detailed observation and analysis of complex software stacks and multicore architectures under the presence of faults at early design phases. The main contribution of this paper relies on the exploration of supervised and unsupervised machine learning (ML) techniques that can be used to identify the correlation between fault injection results and application and platform microarchitectural characteristics.…”

Extensive Evaluation of Programming Models and ISAs Impact on Multicore So Error Reliability

“…Such frameworks provide high simulation performance, design flexibility (e.g., processor, memory, and peripheral models), and several debugging capabilities. Most fault injection simulators that rely on VP support the injection of bitflips in memory and register-file components [6,7,11,16,17,22]. While the work in [17] supports the fault injection into the processor address generation unit, the authors in [7,11,22] explored the impact of injecting bit-flips into the load/store queue.…”

“…Most fault injection simulators that rely on VP support the injection of bitflips in memory and register-file components [6,7,11,16,17,22]. While the work in [17] supports the fault injection into the processor address generation unit, the authors in [7,11,22] explored the impact of injecting bit-flips into the load/store queue. The majority of these works consider either simple (i.e., in-house and bare metal applications) or small scenarios, where only a single-core processor or specific ISA is considered.…”

An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

“…In this work, we find the critical variable using a gemV framework [20], which is the vulnerability estimation toolset for microarchitectural components based on a cycleaccurate gem5 simulator [21]. Since gemV returns the reliability for microarchitectural components such as register file and memory, we have modified gemV to achieve the criticality of source-level variables.…”