Ge/Si Hetero-Junction Hetero-Gate PNPN TFET withHetero-Dielectric BOX to Improve ION/IOFF

Turkane, S. M.; Kharate, G. K.; Kureshi, A. K.

doi:10.17485/ijst/2017/v10i14/95495

Cited by 11 publications

(1 citation statement)

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“…MOSFETs, integral to contemporary electronics, confront inherent challenges, notably sub-threshold leakage currents arising from quantum tunneling, which curtail power efficiency and voltage scaling capabilities. Hence, Tunnel FETs (TFETs) surfaced as potential devices for low power applications [1,2] with attractive properties such as sub-threshold swing [3] below 60 mV/decade, and low OFF currents [4]. The basic working principle of Tunnel FET is band to band tunneling of the charge carriers.…”

Section: Introductionmentioning

confidence: 99%

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

Das,

Dhar,

Ghosh

2023

Phys. Scr.

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This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2-D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10-17 A/µm) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

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