Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

Abstract

─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-processing step that provides an effective set of initial Lagrange multipliers. Compared to the previous Lagrangian-based approach, Forge is considerably faster and does not have the inefficiencies due to difficult-to-determine initial conditions and constant factors. We compared the two algorithms on 30 benchmark designs, on a Sun UltraSparc-60 workstation. On average Forge is 200 times faster than the previously published algorithm. We then improved Forge by incorporating a slew-rate-based convex delay model, which handles distinct rise and fall gate delays. We show that Forge is 15 times faster, on average , than the AMPS transistor-sizing tool from Synopsys, while achieving the same delay targets and using similar total transistor area.

Sensitivity-guided metaheuristics for accurate discrete gate sizing

“…• Linear programming [2,5,17] and network flow [25] • Convex nonlinear optimization [6,26,27,31], including Lagrangian relaxation [4,6,19,30,31] • Slew budgeting [14] Due to the complexity of modern designs, the two most scalable approaches are those based on Lagrangian relaxation and sensitivity. Instead of satisfying every imposed constraint, Lagrangian relaxation changes the original constrained problem into an unconstrained problem such that the solutions to the latter can be mapped back to the former.…”

High-performance gate sizing with a signoff timer

“…It is common to simplify circuit delay models and solve an abstract, continuous version of the problem to facilitate convex optimization -Lagrangian relaxation, linear programming, network flows, etc. [6,10,20,21,25]. Simultaneous gate sizing and V th assignment has shown promising results [23,24].…”

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

“…As with many sizing works, a sensitivity function, such as the ratio of incremental power to incremental delay, is typically used, often along with pre-budgeted timing requirements for each cell or path. Chou et al [15] investigate gate sizing and V th assignment using the Lagrangian relaxation framework previously investigated by [5], [16]. Sarrafzadeh et al [17] present a convex programming based delay budgeting algorithm and use the budgeting results as net length constraints for placement.…”