Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

Abstract

To sustain the silicon CMOS scaling beyond 100nm, an alternate gate dielectric with K > 7 is needed. The deposited high K dielectrics (metal oxides) have nonstoichiometeric composition and therefore have large electrical defects (traps) in the bulk of the dielectric and at the dielectric/semiconductor interface. In this paper, we report a novel doping method to quench traps in thin films of A1203 (K > 8). By adding small amounts of dopants such as Zirconium (Zr) or Silicon (Si), we have achieved -1 Onm thick aluminum oxide films with record low leakage current (< 10 -13A/mm2) and ultra-thin (3-5nm) aluminum oxide films with very low interface state density (-10 "/cm2-eV) at the silicordaluminum oxide interface. We propose a physics based model for the doping effect and selection of dopants for metal oxides with K > 10.

The effect of oxygen source on atomic layer deposited Al2O3 as blocking oxide in metal/aluminum oxide/nitride/oxide/silicon memory capacitors

“…A post metallization annealing was performed at 350°C for 20 min in nitrogen ambient. Transmission electron microscopy (TEM) Thin Solid Films 533 (2013) [5][6][7][8] was employed for the investigation of the gate stack thickness characteristics. TEM studies were performed on a Philips CM 20 microscope with high resolution capabilities, operating at 200 kV, equipped with an energy dispersive X-ray spectrometer (EDS).…”

“…In that direction the siliconoxide-nitride-oxide-silicon memories [3] are particularly attractive but suffer from significant drawbacks such as slow erase operation, insufficient retention characteristics and undesirable electron injection from gate electrode during the application of high negative voltages [4]. High-permittivity (high-k) dielectric materials, such as Al 2 O 3 [5,6], have been proposed as substituent for one or more of the dielectric layers of the oxide-nitride-oxide stack; a substitution of which improves significantly the properties of the memory cell. Al 2 O 3 has excellent chemical and thermal stability [7,8], and a wide band-gap, combined with a moderate permittivity.…”

A Novel Gate Dielectric with ZrxLa1−xOyMaterial for the Future of Nano Transistor Devices

“…These materials exhibit reasonably high dielectric constants of k > 15 without crystallization during typical processing conditions. Zr dopant have also been used in Al 2 O 3 to quench traps and reduce leakage currents [25]. The aim of the present study is to prepare and characterize the properties of Zr x La 1-x O y nanocrystallites using the sol-gel method.…”

Current Tunnelling in MOS Devices with Al2O3/SiO2Bouazra1, Nasrallah2, Saïd3 et al. 2008Research Letters in Physics20070View full textAdd to dashboardCite

“…The SiO 2 gate dielectric thickness is projected to be below 1 nm and the power supply (V dd ) should fall within 0.8 and 1.8 V. In this situation, the gate leakage currents due to tunnelling become very high. Therefore, it has become necessary to use high-k gate dielectrics in order to meet the strict requirements on leakage current and equivalent oxide thickness (EOT) such as HfO 2 [1,2], ZrO 2 [3][4][5][6], TiO 2 [7], and Al 2 O 3 [8,9]. Unfortunately, for most high-k materials, the higher dielectric constant comes at the expense of narrower band gap, 5-6 eV [10], that is, lower barrier height for tunnelling and the lower barrier height tends to compensate the benefit of the higher dielectric constant (thicker dielectric layer).…”