Gate oxide breakdown under Current Limited Constant Voltage Stress

Linder, B.; Stathis, James H.; Wachnik, R.; Wu, Ernest Y.; Cohen, S.; Ray, Abhishek; Vayshenker, A.

doi:10.1109/vlsit.2000.852830

Cited by 71 publications

(32 citation statements)

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“…19. For a current limit less than A, the off current remains small after oxide breakdown, while higher current limits resulted in a wide range of values [172]. Thus it appears that small current limits (corresponding to very small p-FET drivers) halt the breakdown event such that the transistors may still be operational.…”

Section: B Device Breakdownmentioning

confidence: 99%

“…A circuit does not usually subject a gate to either a constant-voltage or a constant-current stress, which are the two types of stress typically employed, but rather to a current-limited stress in which the current through a breakdown spot is limited by the saturation on-current (Idsat) of a complementary transistor in series [172]. Fig.…”

Section: B Device Breakdownmentioning

confidence: 99%

“…Compared to a typical constant voltage source, the small transistor in series has much higher impedance, a much lower current capability, and a lower capacitive loading. To simulate the stress that gate oxides experience during circuit operation, Linder [172] purposely limited the post-breakdown current using the compliance setting of a voltage source or by inserting a transistor between the voltage source and device under test. The compliance level could be set to emulate the saturation current of the drive transistor.…”

Section: B Device Breakdownmentioning

confidence: 99%

“…Fig. 20 shows the post-breakdown conduction measured at V as a function of the stress compliance level [172]. Again there is a transition at about A compliance, corresponding to a series resistance of .…”

Section: B Device Breakdownmentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

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163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: B Device Breakdownmentioning

confidence: 99%

Section: B Device Breakdownmentioning

confidence: 99%

Section: B Device Breakdownmentioning

confidence: 99%

Section: B Device Breakdownmentioning

confidence: 99%

See 2 more Smart Citations

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

Self Cite

163

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show abstract

“…Recently, we have reported a strong post-BD current reduction in MOS capacitors with ultrathin high-k dielectric stacks when the current during the BD transient is limited [2], suggesting that, as sometimes observed for SiO 2 [3][4][5], BD in these devices is a reversible phenomenon. Since a current limited BD can better represent the BD conditions of MOSFETs within circuits [6], the investigation of the impact of the gate BD reversibility on transistors and circuits performance is mandatory. In this work, we report the evidence of two conductivity states after dielectric BD in transistors with ultra-thin high-k dielectric.…”

Section: Introductionmentioning

confidence: 99%