Gate Leakage for 28 nm Stacked HfZrO_{<italic>x</italic>} Dielectric of p-Channel MOSFETs After Decoupled Plasma Nitridation Treatment With Annealing Temperatures

Abstract

Choosing a plasma nitridation treatment with some annealing technique incorporated into the gate engineering is helpful to fix the existence of oxygen vacancy and promote the crystallization temperature in high-k dielectric. Here is the higher annealing atmosphere as a whole providing the better drive current in p-channel metal-oxide-semiconductor fieldeffect transistors, compared with the lower one. The interface traps for the former, however, is slightly greater than the latter, causing a higher gate leakage in the middle electrical field operated at inversion mode. This phenomenon is more obvious in the tested short-channel device. A sandwich type of HfO x /ZrO y /HfO x as gate dielectric at 28 nm node process is a fine selection to withstand or decrease the possibility of the formation of micro-or nanocrystallization increasing the gate leakage.Index Terms-Annealing, decoupled plasma nitridation (DPN), gate leakage, high-k dielectric, MOSFET.

Comparison of electrical characteristics for SiONx and HfZrOx gate dielectrics of MOSFETs with decoupled plasma nitridation treatment

“…Yet, besides these effects, some boron traps assistant will enhance the gate leakage at the pMOSFET. If the traditional maximum limitation of gate leakage, J G = 1 A/cm 2 , for a MOSFET is adopted, the gate leakage from HK MOSFET with Poole-Frenkel tunneling mechanism [21,27,42] discussing the mechanisms of gate leakage from the concentration of nitridation and the temperature annealing in DPN treatment is still necessary to be improved. The possible causes after HK deposition are the more trap amount, nano-crystallization [43] from non-optimal annealing controls or oxygen vacancy.…”

“…Utilizing a stacked structure of HfO x /ZrO y /HfO x (HZH) as a high-K (HK) [14] gate dielectric, it seems a workable way to provide a plentiful high-K [15,16] value fulfilling the drive current concern and constrain some transport charges from channel substrate to gate electrode owing to the lower energy band in ZrO y [17] layer, producing a lower gate leakage [18] as well as the promotion of crystallization temperature [19]. At the same time, the amount of oxygen vacancy [20][21][22] or thickness of the interfacial layer [23] neighboring the surface channel between gate electrode and surface channel probably deteriorates the drive current due to the increase of |V T | or the diminution of effective high-K value, respectively. To suppress this disadvantage or intensify the device integrity, using a low-pressure decoupled plasma nitridation (DPN) process [24][25][26][27] previous drawbacks.…”