Gate-Induced Drain Leakage in Negative Capacitance FinFETs

Gaidhane, Amol D.; Pahwa, Girish; Verma, Amit; Chauhan, Yogesh Singh

doi:10.1109/ted.2020.2967463

Cited by 25 publications

(5 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This results in lower peak amplification, in turn favoring sharper/shallower junctions as with conventional MOSFETs, to minimize short channel effects (SCE). This is consistent with [33] and, in this regime, the NC entitlement is not fully realized. However, in the second regime (Fig.…”

Section: Junction Design Implicationssupporting

confidence: 87%

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Vega¹,

Ando

Philip³

2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DCoptimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same nonhysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

show abstract

Section: Junction Design Implicationssupporting

confidence: 87%

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Vega¹,

Ando

Philip³

2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…The propagation delay of the inverter is about 115 ps at ρ = 0.8 Ω·m. Such large value is definitely not attributed to the loading capacitance at the output, but the additional intrinsic delay of the FE capacitor due to the slower response of the FE dipoles [31]. Compared with ρ = 0.01 Ω·m, t delay dramatically drops to 23 ps.…”

Section: Resultsmentioning

confidence: 99%

“…For V G = 0 V, NCFET inverter consumes 77.3% [ = (3.44 − 0.78)/3.44] less power. This is because the NCFET shows a lower sub‐threshold current compared to the baseline due to the reverse short channel effects induced by fringing field coupling to NC FE [31].…”

Section: Resultsmentioning

confidence: 99%

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

Zhang

Lü

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

“…4(d) shows that the band gap with 2.2×10 18 /cm 3 Nd is narrower than that with 1×10 18 /cm 3 Nd when Tfe equals 25 nm, indicating tunneling current increases with increasing Nd [33]. Moreover, the increase of IOFF also originates from gate-induced drain leakage (GIDL) current [34,35]. shows that as LC increases, the influence of Vd on channel potential is receded, and the NDR effect is weakened.…”

Section: B Output Performancementioning

confidence: 99%

Performance optimization of GaAs NCFET with a complex oxide ferroelectric gate

Jia,

Li,

et al. 2024

Preprint

View full text Add to dashboard Cite

In this work, we try to design a high-performance GaAs NCFET with ferroelectric 0.85BiTi0.1Fe0.8Mg0.1O3-0.15CaTiO3 (BTFM-CTO) gate dielectric. A detailed simulation was first made on GaAs NCFET to clarify the influence of key structural factors on the performance of NCFET. Simulation results indicate these factors have effects on capacitances match. Moreover, key factors will also affect the device performance and result in the variation of some effects such as negative differential resistance (NDR), gate voltage amplification (GVA), short channel effect (SCE), and saturation of carrier mobility (SCM). These effects influence and constraint each other. The competition between these effects makes the performance not monotonously vary with factors and highly depends on other parameters or voltage bias. Mobility, band energy diagram, electric potential along channel surface, and substrate capacitance are then investigated to make detailed analyses of simulation results. These simulation results and analysis are valuable to optimize NCFET and adjust the drive strength of NCFET with a given ferroelectric film, which would benefit the further application of NCFET. Finally, optimization of the NCFET with BTFM-CTO has been done. A steep SS value of 44.9 mV/dec and a high ION/ IOFF value of 1.2×109 is achieved with a low supply voltage of 0.6 V, demonstrating that the BTFM-CTO film is a competitive candidate for a ferroelectric layer applied in GaAs NCFET. The current work may generate new insights into advanced NCFET based on GaAs with high ION/ IOFF.

show abstract

Gate-Induced Drain Leakage in Negative Capacitance FinFETs

Cited by 25 publications

References 35 publications

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

Performance optimization of GaAs NCFET with a complex oxide ferroelectric gate

Contact Info

Product

Resources

About

Gate-Induced Drain Leakage in Negative Capacitance FinFETs

Cited by 25 publications

References 35 publications

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

Performance optimization of GaAs NCFET with a complex oxide ferroelectric gate ​

Contact Info

Product

Resources

About

Performance optimization of GaAs NCFET with a complex oxide ferroelectric gate