Gate Dielectric Chemical Structure−Organic Field-Effect Transistor Performance Correlations for Electron, Hole, and Ambipolar Organic Semiconductors

Abstract

This study describes a general approach for probing semiconductor-dielectric interfacial chemistry effects on organic field-effect transistor performance parameters using bilayer gate dielectrics. Organic semiconductors exhibiting p-/n-type or ambipolar majority charge transport are grown on six different bilayer dielectric structures consisting of various spin-coated polymers/HMDS on 300 nm SiO(2)/p(+)-Si, and are characterized by AFM, SEM, and WAXRD, followed by transistor electrical characterization. In the case of air-sensitive (generally high LUMO energy) n-type semiconductors, dielectric surface modifications induce large variations in the corresponding OTFT performance parameters although the film morphologies and microstructures remain similar. In marked contrast, the device performance of air-stable n-type and p-type semiconductors is not significantly affected by the same dielectric surface modifications. Among the bilayer dielectric structures examined, nonpolar polystyrene coatings on SiO(2) having minimal gate leakage and surface roughness significantly enhance the mobilities of overlying air-sensitive n-type semiconductors to as high as approximately 2 cm(2)/(V s) for alpha,omega-diperfluorohexylcarbonylquaterthiophene polystyrene/SiO(2). Electron trapping due to silanol and carbonyl functionalities at the semiconductor-dielectric interface is identified as the principal origin of the mobility sensitivity to the various surface chemistries in the case of n-type semiconductors having high LUMO energies. Thiophene-based n-type semiconductors exhibiting similar film morphologies and microstructures on various bilayer gate dielectrics therefore provide an incisive means to probe TFT performance parameters versus semiconductor-dielectric interface relationships.

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

“…The sub-threshold swing (s-s) was calculated to be ~1.5 V/decade and the density of traps was estimated to be 1 x 10 13 cm -2 using Eq. 7 54,55 . Maximum current is 1.6mA.…”

Trends in molecular design strategies for ambient stable n-channel organic field effect transistors

“…OTS, OTMS, and HMDS, reduces the number of trapping sites at the SiO 2 /semiconductor interface and enhances n-channel performance. 62,63 These materials render the SiO 2 layer hydrophobic by reacting with the silanol groups (SiOH) present at the surface. Dielectric surface modifiers decrease the surface energy and increase the smoothness of the surfaces which improves the crystallinity of the deposited thin films, increases the grain-sizes, and concomitantly reduces the number of grain boundaries.…”

Remarkable reduction in the threshold voltage of pentacene-based thin film transistors with pentacene/CuPc sandwich configuration

“…[7][8][9][10] To lower power consumption, low V T is a basic requirement. Hence, methods to reduce OTFTs V T have been developed, including the use of ultrathin or high dielectric constant insulators, [11][12][13] the improvement of metal/organic and organic/dielectric interfaces, [14][15][16][17][18][19][20] and the optimization of device configuration. 21,22 A previous study lowered the V T of copper phthalocyanine (CuPc) TFTs from −13.8 V to −8.9 V using a double layer of active organic semiconductors of CuPc and cobalt phthalocyanine in sandwich configuration.…”