Gate‐Defined Quantum Confinement in CVD 2D WS₂

Abstract

metal-oxide-semiconductor field-effect transistors (MOSFETs). As we continue to squeeze the last few drops from the lemon that is Moore's law, alternative channel materials other than silicon will be needed for future devices. [2] Likewise, replacement of traditional dielectrics, silicon oxide, with high-k dielectrics are being implemented for increased gate capacitance with low leakage currents. Currently, state-of-the-art MOSFETs manufactured by Intel utilizes a 2.6 nm thick high-k HfO 2 gate dielectric in their 14-nm FinFET structures. [3] For channel materials, promising candidates are 2D semiconductors such as transition metal dichalcogenides (TMDCs). [4][5][6][7][8][9][10] 2D TMDCs are an important class of atomically thin materials with novel properties such as tunable layer-dependent direct bandgaps, strong photoluminescence, large spin-orbit coupling, and unique spin-valley coupling. [11][12][13][14][15] These exceptional properties are attractive for applications in electronics, optoelectronic and quantum information processing. 2D TMDCs were first isolated with the "Scotch tape" technique, where adhesive tapes "peel" thin flakes from bulk crystals that are then repeatedly exfoliated to a single atomic layer. [16] Devices are fabricated through manual assembly and stacking of such semiconducting or insulating micron Temperature-dependent transport measurements are performed on the same set of chemical vapor deposition (CVD)-grown WS 2 single-and bilayer devices before and after atomic layer deposition (ALD) of HfO 2 . This isolates the influence of HfO 2 deposition on low-temperature carrier transport and shows that carrier mobility is not charge impurity limited as commonly thought, but due to another important but commonly overlooked factor: interface roughness. This finding is corroborated by circular dichroic photoluminescence spectroscopy, X-ray photoemission spectroscopy, cross-sectional scanning transmission electron microscopy, carrier-transport modeling, and density functional modeling. Finally, electrostatic gate-defined quantum confinement is demonstrated using a scalable approach of large-area CVD-grown bilayer WS 2 and ALD-grown HfO 2 . The high dielectric constant and low leakage current enabled by HfO 2 allows an estimated quantum dot size as small as 58 nm. The ability to lithographically define increasingly smaller devices is especially important for transition metal dichalcogenides due to their large effective masses, and should pave the way toward their use in quantum information processing applications.The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.202103907.

Liquid-Metal-Printed Ultrathin Oxides for Atomically Smooth 2D Material Heterostructures

“…Next, we examined the interfaces between WS 2 monolayer and few-layer regions and ultrathin Ga 2 O 3 with cross-sectional STEM imaging (Figure c,d). These images confirm that direct printing produces atomically smooth interfaces, which is critical for reducing interface roughness scattering that lowers carrier mobilities in 2D FETs . High-resolution cross-sectional STEM images (Figure e,f) highlight the interface improvement over conventional ALD growth.…”

“…These images confirm that direct printing produces atomically smooth interfaces, which is critical for reducing interface roughness scattering that lowers carrier mobilities in 2D FETs. 45 Highresolution cross-sectional STEM images (Figure 2e,f) highlight the interface improvement over conventional ALD growth. We observe sub-nm separation for the LM-printed Ga 2 O 3 /WS 2 interface compared to the few-nm voids that line the ALD HfO 2 /WS 2 interface.…”

Quantum Technologies for Engineering: the materials challenge

“…Interestingly, this is also a key recommendation in the recent review by de Leon et al [6]. In what follows, we shall briefly describe the materials development and the associated feedback instrumentation, highlighting the key device fabrication steps leading to the first gate-controlled quantum dot demonstration in 2D TMDC using scalable materials, which is recently reported in a research article [52].…”

“…In particular, the collaboration of Goh's group with Chhowalla's group (Cambridge, UK) exemplifies the leverage afforded by an international collaborative effort to expediently apply the new concept of indium alloy contacts (pioneered in Chhowalla's laboratory) to Goh's quantum devices to achieve record low contact Schottky barriers [59]. These efforts enabled Goh's team to speed up device development culminating in the recently demonstrated gate-controlled quantum dot device in 2D TMDC using scalable materials [62]. While these are encouraging developments, the lack of consistent high-quality large scale 2D TMDCs severely limits reproducibility.…”

“…High quality grown 2D TMDCs are urgently needed and optimised dielectric encapsulation processes that limit the interface traps formed with surrounding dielectrics need to be pursued in a scalable manner. Goh's team recently showed that material interface roughness associated with the dielectric substrate supporting the 2D TMDC can significantly compromise the quantum dot and hence qubit quality [62]. Whilst we do expect valley protection of the spin in these 2D TMDC monolayers, it remains to be seen if isotopic purification of the growth precursors for the TMDC growth and also for the surrounding dielectrics would be required to suppress hyperfine coupling to atoms with non-zero nuclear spins which could decohere the spin-based qubit.…”