Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Waldron, Niamh; Sioncke, Sonja; Franco, J.; Nyns, L.; Vais, Abhitosh; Zhou, Xiaoxin; Lin, Hengwei; Boccardi, G.; Maes, Jan Willem; Xie, Qingyun; Givens, M. E.; Tang, Fu; Jiang, Xiaoqiang; Chiu, E.; Opdebeeck, A.; Merckling, Clément; Sebaai, Farid; Dorp, Dennis van; Teugels, Lieve; Hernandez, Arturo Sibaja; Meyer, K. De; Barla, K.; Collaert, N.; Thean, Y-V.

doi:10.1109/iedm.2015.7409805

Cited by 29 publications

(32 citation statements)

References 5 publications

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“…2) are expected to have clear advantages of subthreshold slope compared to a FinFET device at the same gate length. 5,[25][26][27] Their production promises little deviation from a standard FinFETs processing flow, but a significant improvement of the electrostatic properties. The process scheme of our Si and Ge GAA FETs starts with the deposition of a stack of two materials on blanket wafers (STI-last approach), typically Si/SiGe on Si and SiGe/Ge on graded SiGe-SRBs.…”

mentioning

confidence: 99%

“…[1][2][3][4][5][6][7] These so-called high mobility materials are implemented in new device concepts and novel architectures, for example tunnel FETs and gate-all-around devices, in order to meet the power and performance requirements. Reference 7 gives an overview of the innovations in materials and new device concepts that will be needed to continue Moore's law to sub-7nm technology nodes.…”

mentioning

confidence: 99%

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Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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mentioning

confidence: 99%

mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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“…These improvements on capacitance level are reflected by the electrical metrics on transistor level, as evident from the data in Figure 5. InGaAs FinFET [2] InGaAs QWFET [6] InAs QWFET [7] InGaAs QWFET [8] InGaAs QWFET [9] InAs QWFET [10] InGaAs FinFET [14] InGaAs NWFET [15], [16] This Work…”

Section: Methodsmentioning

confidence: 99%

“…Our InAs nanowire FETs have 7.5% higher figure of merit Q than the current record In 0.53 Ga 0.47 As nanowire FET on a 300 mm Si substrate [16].…”

Section: S (Mv/dec)mentioning

confidence: 97%

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High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates

Doornbos¹,

Holland²,

Vellianitis³

et al. 2016

IEEE J. Electron Devices Soc.

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> To be considered for J-EDS special issue on "Advanced technology for ultra-low power electronic devices" < 1  Abstract-We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully VLSI-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high- dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance g m is 1.65 mS/μm, at V ds of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L g of 90 nm, a nanowire height H NW of 25 nm, and a nanowire width W NW of 20 nm, resulting in Q ≡ g m /S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R sd of 160-200 Ω•μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity v tx of 3-4×10 7 cm/s and backscattering coefficient r c as a function of gate length.Index Terms-High-mobility channel, MOSFET, Nanowires, III-V semiconductor materials.

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Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

Maity

Basak

Das

2022

Int J Numerical Modelling

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Negative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different DC and analog figure of merits such as on current (ION), switching ratio (ION/IOFF), threshold voltage roll‐off, sub‐threshold swing (SS), trans‐conductance (gm), transconductance efficiency (gm/ID) of the test device has been analyzed for different ferroelectric layer thicknesses and compared with the baseline device. We have investigated RF performance such as gate capacitance, unity‐gain cut‐off frequency and small signal voltage gain of the device. Improvement in DC and analog figure of merits is proportional to the ferroelectric layer thickness. However, for higher values of ferroelectric thickness, the hysteresis effect gradually became prominent. MOS transistor with optimum ferroelectric layer thickness shows the negligible amount of threshold voltage roll‐off and improved transconductance‐frequency product compared to the baseline device. In presence of ferroelectric layer, the effect of channel thickness variation on device performance is reduced. The role of ferroelectric gate stack is found to be more prominent at shorter gate length.

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Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Cited by 29 publications

References 5 publications

Processing Technologies for Advanced Ge Devices

Processing Technologies for Advanced Ge Devices

High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates

Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

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