GANGLION-a fast field-programmable gate array implementation of a connectionist classifier

Cox, Charles E.; Blanz, W. E.

doi:10.1109/4.121550

Cited by 110 publications

(35 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…ANNs with different structures and synaptic parameters targeting different applications can be loaded on the FPGA via runtime reconfiguration. One of the earliest implementations of artificial neural networks on FPGAs, the Ganglion connectionist classifier, used FPGA reconfigurations to load networks with different structures for each new application of the classifier [50]. Similar approaches of using runtime reconfiguration to retarget the FPGA for different ANN applications are found in [22, 25-31, 51, 52].…”

Section: Designmentioning

confidence: 98%

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Merchant

Peterson

2010

VLSI Design

View full text Add to dashboard Cite

Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.

show abstract

Section: Designmentioning

confidence: 98%

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Merchant

Peterson

2010

VLSI Design

View full text Add to dashboard Cite

show abstract

“…Hence, iterative construction of ANNs can be realized through topology adaptation. A digital architecture for classification using FPGAs' re-programmability feature is described in [64].…”

Section: Fpgamentioning

confidence: 99%

Hardware Design for Machine Learning

Jawandhiya¹

2018

IJAIA

View full text Add to dashboard Cite

show abstract

“…Even though most RCs are considered dynamic, several static RCs exist. For example, GANGLION [8] is a connectionist classifier used in manufacturing for identifying edges and objects. Static RCs include the MacTester [11], iPoint [18], and SeeD-ROM [20].…”

Section: Static Rcsmentioning

confidence: 99%

Reconfigurable and Adaptive Computing Environments

Bhatia¹

2000

View full text Add to dashboard Cite

GANGLION-a fast field-programmable gate array implementation of a connectionist classifier

Cited by 110 publications

References 5 publications

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Hardware Design for Machine Learning

Reconfigurable and Adaptive Computing Environments

Contact Info

Product

Resources

About