2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) 2018
DOI: 10.1109/dac.2018.8465816
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GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets

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Cited by 41 publications
(59 citation statements)
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“…Recently, GANs [10] have shown promising potential in many applications, including image processing, computer vision, and design for manufacturability, etc. [11,12]. A conventional GAN architecture is diagrammed in Fig.…”
Section: Gan-based Well Guidance Creationmentioning
confidence: 99%
“…Recently, GANs [10] have shown promising potential in many applications, including image processing, computer vision, and design for manufacturability, etc. [11,12]. A conventional GAN architecture is diagrammed in Fig.…”
Section: Gan-based Well Guidance Creationmentioning
confidence: 99%
“…Chen et al used Auto Pattern Selection (APS) tool to train the Newron SRAF deep learning network and successfully realized the inverse mask optimization on full-chip layout [23] . As examples, this section will detail two ILT methods based on variational autoencoder (VAE) [24] and generative adversarial network (GAN) [25] .…”
Section: Ilt Based On Standard Deep Learningmentioning
confidence: 99%
“…The (a) workflow and the (b) simulation results of the proposed GAN-OPC method (adopted from Figs. 6 and 8 in Ref [25]…”
mentioning
confidence: 99%
“…VLSI layout patterns are significant resources for flows of various design for manufacturability (DFM) research, such as optical proximity correction (OPC) [7,10,13,15,26], layout hotspot detection [5,27,30,33,34], pattern matching [4], lithography simulation [16,17,31] and so on. However, VLSI layout pattern libraries are very often not available for research or testing due to the long and iterative technology life cycle, especially in the initial stage, which may slow down the technology node development [10].…”
Section: Introductionmentioning
confidence: 99%