GaN/AlN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-current

“…The same issues are also expected to arise if the polarity of the films are flipped, and a 2DEG is generated at the GaN/AlN interface on N-polar AlN buffer layer. With the rising relevance of AlN as the platform for UV photonics and future RF electronics 8,28 , significant interest exists in using 2DEGs and 2DHGs on AlN to make RF p-channel 7,29 and n-channel transistors 30,31 and enable wide-bandgap RF CMOS type devices. Combining the results of this work with recent advancements in homoepitaxial growths of AlN 32,33 should enable fundamental scientific studies of 2DEGs and 2DHGs in such polar heterostructures and simultaneously enable significant technological advances.…”

Section: Discussionmentioning

confidence: 99%

High conductivity Polarization-induced 2D hole gases in Undoped GaN/AlN Heterojunctions enabled by Impurity Blocking Layers

Chaudhuri,

Chen,

Muller

et al. 2021

Preprint

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High-conductivity undoped GaN/AlN 2D hole gases (2DHGs), the p-type dual of the AlGaN/GaN 2D electron gases (2DEGs), have offered valuable insights into hole transport in GaN and enabled the first GaN GHz RF p-channel FETs. They are an important step towards high-speed and high-power complementary electronics with wide-bandgap semiconductors. These technologically and scientifically relevant 2D hole gases are perceived to be not as robust as the 2DEGs because structurally similar heterostructures exhibit wide variations of the hole density over ∆p s > 7 × 10 13 cm −2 , and low mobilities. In this work, we uncover that the variations are tied to undesired dopant impurities such as Silicon and Oxygen floating up from the nucleation interface. By introducing impurity blocking layers (IBLs) in the AlN buffer layer, we eliminate the variability in 2D hole gas densities and transport properties, resulting in a much tighter-control over the 2DHG density variations to ∆p s ≤ 1 × 10 13 cm −2 across growths, and a 3× boost in the Hall mobilities. These changes result in a 2-3× increase in hole conductivity when compared to GaN/AlN structures without IBLs.

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“…However, the challenges of the monolithic integration of the p-type GaN FETs with n-type GaN FETs along with lack of high-performance of p-type GaN FETs are the major obstacle towards achieving high efficiency GaN-based ICs. A various epitaxial structures of p-type GaN FETs have been demonstrated [110][111][112][113][114][115][116][117]. A GaN complementary inverter circuit comprising of both E-mode n-type GaN FET and p-type GaN FET monolithically integrated on Si Substrate without regrowth technology was also demonstrated [118].…”

Section: Gan-based Cmos Technologymentioning

confidence: 99%

“…The fabricated circuit shows an outstanding transfer characteristics up to 300 • C with maximum recorded voltage gain of about 27 V/V at 0.59 V input voltage with 5 V as V DD supply. A very high density of 2D hole gas (2DHG) induced by the polarization at the interface of GaN/AlN was discovered [119] which led to the development of p-channel heterostructure field effect transistors (HFETs) that reach the linear current density of 100 mA/mm [112]. A p-channel MISFET with a recessed-gate was grown by metalorganic chemical vapor deposition (MOCVD) using p-GaN/AlGaN/GaN hetrostructure on Si substrate [113,118].…”

Section: Gan-based Cmos Technologymentioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

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GaN/AlN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-current

Cited by 27 publications

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Tungsten-Gated GaN/AlGaN p-FET With I_max > 120 mA/mm on GaN-on-Si

Tungsten-Gated GaN/AlGaN p-FET With I_max > 120 mA/mm on GaN-on-Si

High conductivity Polarization-induced 2D hole gases in Undoped GaN/AlN Heterojunctions enabled by Impurity Blocking Layers

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

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GaN/AlN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-current

Cited by 27 publications

References 0 publications

Tungsten-Gated GaN/AlGaN p-FET With Imax > 120 mA/mm on GaN-on-Si

Tungsten-Gated GaN/AlGaN p-FET With Imax > 120 mA/mm on GaN-on-Si

High conductivity Polarization-induced 2D hole gases in Undoped GaN/AlN Heterojunctions enabled by Impurity Blocking Layers

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

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Product

Resources

About

Tungsten-Gated GaN/AlGaN p-FET With I_max > 120 mA/mm on GaN-on-Si

Tungsten-Gated GaN/AlGaN p-FET With I_max > 120 mA/mm on GaN-on-Si