GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

Abstract

The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Current architectures for processors that run security applications are optimized for either high-performance or low energy consumption. We propose an implementation for an architecture that not only provides high performance and low energy consumption but also mitigates security attacks on the cryptographic algorithms which are running on it. The proposed architecture of the GloballyAsynchronous Locally-Synchronous-based Low Power Security Processor (GALS-based LPSP) inherits the scheduling freedom and high performance from the dataflow architectures and the low energy consumption and flexibility from the GALS systems. In this paper, a prototype of the GALS-based LPSP is implemented as a soft core on the Virtex-5 (xc5-vlx155t) FPGA. The architectural features that allow the processor to mitigate Side-Channel attacks are explained in detail and tested on the current encryption standard, the AES. The performance analysis reveals that the GALS-based LPSP achieves two times higher throughput with one and a half times less energy consumption than the currently used embedded processors.

Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm

“…The architecture of the novel crypto processor proposed previously [22] , [23] inherits features both from the transport-triggered paradigm and the dataflow paradigm. Thus, instructions control the bypass circuits rather than the FUs; the FU operation is triggered by the presence of its operands; and the results are passed between the FUs instead of returning back to a register file.…”

“…Any security algorithm can be encoded in an assembly code written using instructions that have a standardized format. As described in [22] , [23] , each instruction specifies the FU responsible for executing the operation and the FU(s) to which the outcome should be forwarded. One instruction can identify one or two destination FUs.…”

“…In [23] the distribution of FUs over four regions was heuristically selected based on execution time of FUs, the communication frequency between the execution regions, and the communication frequency within the Instruction Region. However, other performance issues, such as area and energy consumption were not considered.…”

“…A novel data flow-oriented Crypto Processor based on the Transport Triggered Architecture (TTA) was proposed [22] , [23] . The architecture comprised Function Units (FUs) which were selected to cover all arithmetic/logic functions typically encountered in encryption/decryption algorithms.…”