Gallium Nitride based 3D integrated non-isolated point of load module

Overview of three-dimension integration for Point-of-Load converters

“…In LGA package, GaN bare die is directly packaged with solder bumps underneath and with interleaving drain and source pads to minimize parasitics. Comparing with the packaging methods for 30V trench MOSFET, the LGA package for GaN device has both smaller Ls and L d [4]. To demonstrate the impact of package parasitics, [4] also compared different device packaging methods in a buck converter.…”

“…Comparing with the packaging methods for 30V trench MOSFET, the LGA package for GaN device has both smaller Ls and L d [4]. To demonstrate the impact of package parasitics, [4] also compared different device packaging methods in a buck converter. In order to make a fair comparison of the loss performance between different packaging methods, the analysis in [4] shown that by changing from the SO8 package to the LFPAK, the package-related loss can be greatly reduced due to the smaller parasitic inductance.…”

“…To demonstrate the impact of package parasitics, [4] also compared different device packaging methods in a buck converter. In order to make a fair comparison of the loss performance between different packaging methods, the analysis in [4] shown that by changing from the SO8 package to the LFPAK, the package-related loss can be greatly reduced due to the smaller parasitic inductance. However, the package related loss is still a dominant part of the total loss in LFPAK.…”

“…In order to further increase the switching frequency to shrink the size of passive components, [5] used EPC's GaN device to design 3D integrated POL converters. Because today's 30-40V GaN devices already have very good package (LGA package), [5] directly put GaN devices on the surface of active layer to simplify the fabrication process. [5] also proposed several methods to minimize parasitic loop inductance.…”

“…Then, CPES also proposed several methods, such as embedding bare die devices into active layer, building shielding layer to reduce parasitic inductance of active layer. Furthermore, the GaN high electron mobility transistor (HEMT) was also evaluated and packaged for 3D integrated POL converter to help further increasing switching frequency [4]- [6]. The detailed information about high frequency active layer developed by CPES will be introduced in section III.…”