GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

Ke, Jhih-Ying; Santos Tolentino, Lean Karlo; Lo, Cheng-Yao; Lee, Tzung-Je; Wang, Chua-Chin

doi:10.1109/aicas59952.2024.10595891

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS) 2024

DOI: 10.1109/aicas59952.2024.10595891

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GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

Jhih-Ying Ke,

Lean Karlo Santos Tolentino,

Cheng-Yao Lo

et al.

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GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

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