G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs

Liu, Zhenhong; Gilani, Syed Zohaib; Annavaram, Murali; Kim, Nam Sung

doi:10.1109/hpca.2017.51

Cited by 15 publications

(3 citation statements)

References 21 publications

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“…Several works show that there are some GPU applications with considerable scalar execution, in which the same instruction is executed on the same operands, or almost the same operands [84], among threads in a warp [30,63,83,84]. Based on this observation, these works modify the GPU execution pipeline to support scalar execution.…”

Section: Related Workmentioning

confidence: 99%

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Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

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Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP, a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period M. Sadrosadati performed part of this work at ETH Zürich. L. Orosa was supported by FAPESP fellowship 2016/18929-4.

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Section: Related Workmentioning

confidence: 99%

“…CPU and DRAM power management. Several works apply PG and voltage/frequency scaling in the context of CPUs [17,22,24,31,34,35,[62][63][64][65]79] and DRAM [16,22,23]. Power management techniques in such other contexts cannot be simply applied to GPUs.…”

Section: Related Workmentioning

confidence: 99%

Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

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“…Other related work has investigated augmenting the GPU ISA with new instructions to improve efficiency. One such work leverages fused integer instructions, warp-shared scalar instructions, and SIMD integer datapaths (Gilani et al 2013), while another focuses on leveraging scalar datapaths in GPUs (Liu et al 2017). Another research proposal leverages affine value structure properties inherent in many SIMT applications to design a new GPU ISA with warp-wide scalar instructions .…”

Section: Related Workmentioning

confidence: 99%

Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs

Crago

Stephenson

Keckler

2018

ACM Trans. Archit. Code Optim.

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Modern computing workloads often have high memory intensity, requiring high bandwidth access to memory. The memory request patterns of these workloads vary and include regular strided accesses and indirect (pointer-based) accesses. Such applications require a large number of address generation instructions and a high degree of memory-level parallelism. This article proposes new memory instructions that exploit strided and indirect memory request patterns and improve efficiency in GPU architectures. The new instructions reduce address calculation instructions by offloading addressing to dedicated hardware, and reduce destructive memory request interference by grouping related requests together. Our results show that we can eliminate 33% of dynamic instructions across 16 GPU benchmarks. These improvements result in an overall runtime improvement of 26%, an energy reduction of 18%, and a reduction in energy-delay product of 32%. CCS Concepts: • Computer systems organization → Parallel architectures;

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