Fundamentals of Ion Implantation Technologies for Image Sensing Devices

Fuse, G.; Sugitani, M.

doi:10.1149/06001.0675ecst

Cited by 7 publications

(16 citation statements)

References 5 publications

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“…Otherwise, residual defects are transformed to be new kind of defects during thermal treatment processes in the Back End of Line for Si device' manufacturing (300-600 • C). They may cause the crucial problems of the device's performance, especially for the CCD and/or CMOS image sensors [8], [9]. Notably, if the top temperature of additional FA is set at 700 • C, the diffusion of impurities is not so much, that is, not enough to be a problem with the devices.…”

Section: Discussionmentioning

confidence: 99%

“…These defects were identified as small numbers of point defects. However, they may cause the crucial problems of the device's performance, especially for the CCD and/or CMOS image sensors [8], [9]. These image sensors are mainly fabricated by low-dose implantation processes, and their properties are quite sensitive to the crystal defects due to their scattering of carriers.…”

Section: Introductionmentioning

confidence: 99%

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Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted Silicon After High-Temperature Rapid Thermal Annealing

Sagara

Uedono

Shibata

2015

IEEE Trans. Semicond. Manufact.

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We investigated the thermal behavior of defects remaining in low-dose (<10 13 cm −2 ) arsenic-and boronimplanted Si after high-temperature (1100 • C) rapid thermal annealing (RTA). The defects remaining after RTA were characterized as vacancy-type defects, and confirmed to be created by nonequilibrium states that occur during the extremely rapid cooling step of the RTA sequence. They were gradually removed by applying additional furnace annealing (FA) (i.e., thermal equilibrium heating process) at 300-400 • C. At the range of 500-600 • C, however, carbon-and oxygen-related point defects were newly created. These defects were confirmed to be eliminated at 700 • C, and the crystal quality was significantly improved. When using a rapid thermal process for heat treatment after low-dose impurity implantation, it is necessary to apply an equilibrium thermal treatment at >700 • C to remove residual damage as well as to activate impurities.Index Terms-Residual damage, ion implantation, rapid thermal annealing (RTA), silicon.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted Silicon After High-Temperature Rapid Thermal Annealing

Sagara

Uedono

Shibata

2015

IEEE Trans. Semicond. Manufact.

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“…Figure 5 shows examples of metal contamination measurement by ICPMS (inductively coupled plasma mass spectrometry) [ 17 ]. The samples are about 1 µm thick surface layers to which 2 × 10 16 cm −2 arsenic (As) atoms are implanted with 80 keV energy.…”

Section: Metal Contaminationmentioning

confidence: 99%

“…Although most of the physisorbed metals are washed out by a following cleaning process, some of them invade the silicon by thermal diffusion or knock-on. To learn about the knock-on effect, Figure 7 shows the knocked-on aluminum depth profiles by Monte Carlo simulation [ 17 ]. The condition is that after a 3 nm thick aluminum layer is deposited on the silicon wafer, 1 × 10 15 cm −2 As with two different energies, 50 keV and 1 MeV, is implanted.…”

Section: Metal Contaminationmentioning

confidence: 99%

A Review of Ion Implantation Technology for Image Sensors †

Teranishi

Fuse

Sugitani

2018

Sensors

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Ion implantation technology is reviewed mainly from the viewpoint of image sensors, which play a significant role in implantation technology development. Image sensors are so sensitive to metal contamination that they can detect even one metal atom per pixel. To reduce the metal contamination, the plasma shower using RF (radio frequency) plasma generation is a representative example. The electrostatic angular energy filter after the mass analyzing magnet is a highly effective method to remove energetic metal contamination. The protection layer on the silicon is needed to protect the silicon wafer against the physisorbed metals. The thickness of the protection layer should be determined by considering the knock-on depth. The damage by ion implantation also causes blemishes. It becomes larger in the following conditions if the other conditions are the same; a. higher energy; b. larger dose; c. smaller beam size (higher beam current density); d. longer ion beam irradiation time; e. larger ion mass. To reduce channeling, the most effective method is to choose proper tilt and twist angles. For P+ pinning layer formation, the low-energy B+ implantation method might have less metal contamination and damage, compared with the BF2+ method.

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“…With rapid CIS developments, the photodiode structure evolved from the early planar pinned photodiode (PPD) [1,2] to the current deep PPD [3], proposed to address the backside illuminated (BSI), high-resolution image sensor market. Even so, this technology is limited by the need to employ ion implantation that can cause crystal damage and metal contamination [4,5]. Indeed, to meet high-resolution imaging requirements, shrinking the pixel size led to space search in silicon depth for the storage of photo-generated charges.…”

Section: Introductionmentioning

confidence: 99%

Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

Roy

Suler

Dalleau

et al. 2020

Sensors

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Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

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Fundamentals of Ion Implantation Technologies for Image Sensing Devices

Cited by 7 publications

References 5 publications

Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted Silicon After High-Temperature Rapid Thermal Annealing

Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted Silicon After High-Temperature Rapid Thermal Annealing

A Review of Ion Implantation Technology for Image Sensors †

Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

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