Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures

Roy, Saion K.; Patil, Ameya; Shanbhag, Naresh R.

doi:10.1109/iscas48785.2022.9937336

Cited by 5 publications

(6 citation statements)

References 28 publications

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“…• Finally, we quantify the energy-SNDR trade-off at the bank-level and the energy-accuracy trade-off at the system level for a ResNet-20 (CIFAR-10) and find that the IMC design parameters that maximize the bank-level SNDR are close to those that maximize the network level accuracy. This result, which is consistent with the findings for crossbars [34], indicates that SNDR is a universal bank-level compute accuracy metric that IMC designers can optimize for.…”

Section: Introductionsupporting

confidence: 89%

“…Recognizing this issue, there has been some work on analyzing the compute accuracy of resistive IMCs focusing primarily on resistive crossbars [26]- [34]. Recently, resistive parallel-bar IMCs have become the de-facto standard when designing complete large-scale IMC systems [1]- [14] due to the ease of scalability afforded by the intrinsic isolation between ADC columns.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we propose a compute signal-to-noise-plusdistortion ratio (SNDR) metric to quantify the bank/arraylevel compute accuracy of a resistive parallel-bar IMC (henceforth referred to as resistive IMC). Our previous work [34] indicates that such a metric is predictive of network-level accuracy and has the potential to generalize across tasks.…”

Section: Introductionmentioning

confidence: 99%

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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Roy,

Shanbhag

2024

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This paper proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of MRAM, ReRAM, and FeFET-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAMbased IMC prototype in a 22 nm process. At high output signal magnitude, we find that the maximum achievable SNDR is limited by the pre-ADC array non-idealities such as the conductance variations, parasitic resistances, and current mirror mismatch, whereas the ADC thermal noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions (N > 50), the maximum achievable SNDR is highest for FeFET, followed by ReRAM, and then MRAM. Finally, the increase in conductance contrast (g on /g off ) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18 dB-to-22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5 % when mapping a ResNet-20 (CIFAR-10) by ReRAMbased architecture at a SNDR of 22 dB, which MRAM and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic and learning-based methods, to improve the inference accuracy of resistive IMC architectures.

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Section: Introductionsupporting

confidence: 89%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Roy,

Shanbhag

2024

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…This result can be viewed as a future research opportunity or may indicate a fundamental limitation of eNVM-based IMCs. Our preliminary work in [98] indicates the latter to be the case for resistive crossbars because the input DAC mismatch and the input signal have the same transfer-function. This finding is supported by recent crossbar IMCs [61], [70] that allocate 80% of the bank area to the sensing circuitry/peripherals.…”

Section: A Energy Efficiency Vs Compute Densitymentioning

confidence: 89%

“…The compute SNR SNR col is suggested as a local bank-level metric that IMC designers can measure and report. In fact, recent work [98] shows that bank level compute SNR is a good proxy for network level accuracy, i.e., if IMC designers optimize the ADC column SNR, they can be assured that the network accuracy will be high as well. 5) Network accuracy needs to be accompanied by the associated confidence level and confidence interval to quantify its statistical significance.…”

Section: Summary and Discussionmentioning

confidence: 99%

Benchmarking In-Memory Computing Architectures

Shanbhag

Roy

2022

IEEE Open J. Solid-State Circuits Soc.

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In-memory computing (IMC) architectures have emerged as a compelling platform to implement energy efficient machine learning (ML) systems. However, today, the energy efficiency gains provided by IMC designs seem to be leveling off and it is not clear what the limiting factors are. The conceptual complexity of IMCs combined with the absence of a rigorous benchmarking methodology makes it difficult to gauge progress and identify bottlenecks in this exciting field. This paper presents a benchmarking methodology for IMCs comprising: 1) a compositional view of IMCs that enables one to parse an IMC design into its canonical components; 2) a set of benchmarking metrics to quantify the performance, efficiency, and accuracy of IMCs; and 3) a strategy for analyzing the reported IMC data and metrics. We apply the proposed benchmarking methodology on an extensive database of IMC metrics extracted from > 70 IC designs published since 2018, in order to infer and comprehend trends in this area.Our benchmarking effort indicates: 1) SRAM-based IMCs show a clear win in terms of energy efficiency and compute density over digital accelerators at the bank-level but the energy efficiency gap reduces dramatically when comparing at the processor level; 2) eNVM-based IMCs lag behind SRAM-based IMCs in terms of both energy efficiency and compute density, and surprisingly lag digital accelerators in terms of compute density; 3) the compute (bank-level) accuracy of IMCs, though a critical metric, is pervasively neglected in publications as is the energy vs. accuracy trade-off inherent to IMCs.

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