Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

Victor, D. W.; Ludden, John M.; Peterson, Richard D.; Nelson, B. S.; Sharp, W. K.; Hsu, James; Chu, B.-L.; Behm, Michael; Gott, R.M.; Romonosky, A D.; Farago, S. R.

doi:10.1147/rd.494.0541

Cited by 22 publications

(7 citation statements)

References 9 publications

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“…Instruction by instruction (IBI) checking, or golden model based validation, is a well known checking technique that has been used in processor verification for many years [9,13]. IBI compares the architectural events produced by each executed instruction with those required by the processor specification.…”

Section: Ibi Backgroundmentioning

confidence: 99%

“…These results are usually obtained using a software that can calculate the expected results after each instruction, known as a golden model. Then the checker environment compares these results to the ones produced by the processor simulator for the same test program [9,13]. The checker environment needs to identify when an instruction execution completes and what resources were modified because of the instruction execution.…”

Section: Ibi Backgroundmentioning

confidence: 99%

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Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible.To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.

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Section: Ibi Backgroundmentioning

confidence: 99%

Section: Ibi Backgroundmentioning

confidence: 99%

Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…Unit-level testbenches help identify initial bugs [Shimizu et al 2006]. MP test programs simulated on multicore RTL models expose subtle memory subsystem bugs [Victor et al 2005], and multiple checkers help validate design correctness. Cosimulations against a golden software reference model enable checking of the MP program flow and memory updates Taylor et al 2001].…”

Section: Multicore Verificationmentioning

confidence: 99%

Targeted random test generation for power-aware multicore designs

Singh

Narayanan

Landis

2012

ACM Trans. Des. Autom. Electron. Syst.

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Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre-and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage. ACM Reference Format:Singh, P., Narayanan, V., and Landis, D. L. 2012. Targeted random test generation for power-aware multicore designs.

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“…In [9] the authors describe the functional verification of a POWER5 processor. They use a coarse grained memory-trace mechanism that is well suited for system-level verification.…”

Section: Related Workmentioning

confidence: 99%

A Synchronization Method for Register Traces of Pipelined Processors

Dreesen

Jungeblut

Thies

et al. 2009

IFIP Advances in Information and Communication Technology

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Abstract. During a typical development process of an embedded application specific processor (ASIP), the architecture is implemented multiple times on different levels of abstractions. As a result of this redundant specification, certain inconsistencies may show up. For example, the implementation of an instruction in the simulator may differ from the HDL implementation. To detect such inconsistencies, we use register trace comparison. Our key contribution is a generic method for systematic trace synchronization. Therefore, we convert a micro-architectural trace into an architectural trace. This method considers pipeline hazards and non-uniform write latencies. To simplify the validation of a processor, we further have implemented an automatic validation environment that includes a tool which points the developer directly to erroneous instructions. The flow has been validated during the development of our CoreVA architecture for mobile applications.

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Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

Cited by 22 publications

References 9 publications

Checking architectural outputs instruction-by-instruction on acceleration platforms

Checking architectural outputs instruction-by-instruction on acceleration platforms

Targeted random test generation for power-aware multicore designs

A Synchronization Method for Register Traces of Pipelined Processors

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