Functional timing analysis using ATPG

Ashar, Pranav; Malik, Sharad; Rothweiler, S.G.

doi:10.1109/edac.1993.386424

Cited by 10 publications

(6 citation statements)

References 8 publications

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“…1 Equations (2) and (3) were considered in [18] as exact and approximative circuit delay computation, respectively, even though (3) is in fact exact [14]. The recursive definition of χ f,≥t naturally translates to a combinational circuit.…”

Section: A Maximum Delay For Signal Steadinessmentioning

confidence: 99%

“…Whereas the former is incomplete in that not every delay path can be concluded true or false regardless of arbitrary delay assignments, this paper focuses on the latter analysis. When the underlying computation engine is concerned, an FTA algorithm can be equipped with an automatic test pattern generator, e.g., [1], [6], or by a satisfiability (SAT) solver, e.g., [9], [13], [18]. Since ATPG-based computation involves sophisticated circuit transformation and multifault testing, it is difficult to implement and scale.…”

Section: Introductionmentioning

confidence: 99%

“…Many FTA algorithms, e.g., [1], [3], [5], [6], [9], [10], [13], [14], [16], [18], have been proposed. When delay dependency is concerned, an FTA algorithm can be delay independent [5] or delay dependent [3].…”

Section: Introductionmentioning

confidence: 99%

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Functional Timing Analysis Made Fast and General

Chung¹,

Jiang

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In contrast to structural timing analysis, functional timing analysis for circuit delay computation is accurate, but computationally expensive in refuting false critical paths. Despite recent progress on satisfiability-based functional timing analysis, the formulation generality and computation efficiency remain room for further improvement. This paper provides a unified view on different notions of timed characteristic functions and efficient transformation for satisfiability solving. Experimental results show that functional timing analysis on industrial designs can be made up to several orders of magnitude faster and more generally applicable than prior methods.

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Section: A Maximum Delay For Signal Steadinessmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Functional Timing Analysis Made Fast and General

Chung¹,

Jiang

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, several previous works reported that timed ATPG was unscalable using the PODEM method of implementation. In [1] [8], they show that timed ATPG cannot handle large circuits even though the results are the best among non-timed ATPG approaches such as simulated annealing and genetic algorithms.…”

Section: Introductionmentioning

confidence: 99%

Efficient Boolean Characteristic Function for Fast Timed ATPG

Kuo¹,

Chang²,

Chang³

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Circuit timing analysis is important in various aspects of circuit optimization. The problem of finding input vectors achieving functional and temporal requirements is known as timed Automatic Test Pattern Generation (timed ATPG). A timed ATPG algorithm will return an input vector that satisfies functional and temporal requirements simultaneously when evaluated. Several previous works use timed ATPG as a core engine for solving problems related to timing analysis, such as crosstalk and maximum instantaneous current analysis. Despite the usefulness of timed ATPG, traditional timed ATPG is slow and unscalable for large circuits. In this paper, we present a very efficient way for timed ATPG. On average, our results are 8 times faster than the most recent work, and in some cases, up to 32 times faster.

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“…Binary Decision Diagram(BDD)-based model checking and bounded SAT techniques were used at resolving false paths in synthesized logic blocks in [7]. In [1], ATPG techniques are used to remove false paths during timing analysis while expensive circuit modification technique is performed to resolve re-convergent fanout. In [8], a path delay fault identification prototype tool is used to determine circuit stabilization time.…”

mentioning

confidence: 99%

False timing path identification using ATPG techniques and delay-based information

Zeng

Abadir

Abraham

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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A well-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently [6],[9], as well as how to bridge the gap between the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths [9]. In this paper, we will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PowerPC T M 1 instruction set architecture.

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Functional timing analysis using ATPG

Cited by 10 publications

References 8 publications

Functional Timing Analysis Made Fast and General

Functional Timing Analysis Made Fast and General

Efficient Boolean Characteristic Function for Fast Timed ATPG

False timing path identification using ATPG techniques and delay-based information

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