Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking

Gent, Kelson; Hsiao, Michael S.

doi:10.1109/ats.2013.51

Cited by 14 publications

(3 citation statements)

References 11 publications

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“…The most recent upsurge in publications has started on 2013. As an example, these recent publications mostly focused on fault independent test generation and coverage directed test generation techniques [19,20]. We can observe a decrease in the number of publications from 2015 onward.…”

Section: Publication Trendsmentioning

confidence: 87%

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Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Vivekananda

Enoiu

2020

Designs

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Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

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Section: Publication Trendsmentioning

confidence: 87%

“…Gent et al [20] proposed a method for test generation at the RT level. This method uses a combination of a stochastic search technique and a deterministic search aimed for RTL design validation.…”

Section: Test Levelmentioning

confidence: 99%

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Vivekananda

Enoiu

2020

Designs

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“…Along the direction of simulation based approaches, an approach for the rapid automated validation of an ultralow latency digital core [96] and polychrony based approach for the simulation at system level [97] has been developed. Along the direction of test generation, a swarm intelligence and bounded model checking based approach for functional testing [98], a coverage directed approach by machine learning [99], and an approach for test packet generation [100] were established.…”

Section: Analysis Simulation Verification and Correctionmentioning

confidence: 99%

Machine learning based automated evaluation of piping design

Tan¹

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The contributions of the co-authors are as follows: • Under supervision and guidance from the three co-authors, I collected data and created the dataset, developed the methodology, implemented the idea and wrote the paper. • Professor Chen I-Ming provided guidance on the use of deep learning in automation, pointed out the difference compared to deep learning related research in the domain of computer vision and highlighted the need to go beyond a binary classification. He also reviewed and provided constructive comments to various versions of the paper. • Dr. Dimitrios Pantazis was involved extensively in various discussions on the problem and an important improvement of the idea came up in a discussion with him. • Assistant Professor Sinno Jialin Pan provided guidance as an expert on deep and transfer learning, validated the approach theoretically and practically, reviewed and edited various versions of the paper.

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An Implementation Framework for Optimizing Test Case Generation Using Model Checking

Chang

Miao

Gongzheng³

2015

Structured Object-Oriented Formal Language and Method

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Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking

Cited by 14 publications

References 11 publications

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Machine learning based automated evaluation of piping design

An Implementation Framework for Optimizing Test Case Generation Using Model Checking

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