Functional Criticality Analysis of Structural Faults in AI Accelerators

Chaudhuri, Arjun; Talukdar, Jonti; Chakrabarty, Krishnendu

doi:10.1109/tcad.2022.3166108

Cited by 5 publications

(4 citation statements)

References 25 publications

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“…Software-level [57], [58], [61]- [63], [66]- [91] RTL-level [92], [93] Microarchitectural-level [94] Gate-level [95]- [98] Transistor-level [99], [100] Chip-level [101]- [110] Radiation experiments [81]- [85], [111]- [114] Memristor crossbar-based architectures [115]- [118] oretical study is presented for Feed-Forward Neural Networks (FFNNs) deducing the number of failing neurons and synapses an FFNN can tolerate.…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

“…In [97], [98], ML-based frameworks are proposed for analyzing the functional criticality of gate-level stuck-at faults in systolic array based AI accelerators. Fault injection targets not only the interface/boundary level of a PE, but also all internal nodes of a PE.…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

“…The basic idea is based on the use of deep learning to predict fault criticality by utilizing the structural and data flow features. For example, in [98], a twotier DNN-based model is presented, as illustrated in Fig. 12.…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

“…RTL-level, microarchitectural-level, gate-level, and transistor-level fault injection takes into consideration the Fig. 12: ML-based method for criticality assessment [98].…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

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Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Liu

Stratigopoulos³

2023

IEEE Des. Test

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In recent years, there has been an expedited trend in embracing bold and radical innovation of computer architectures, aiming at the continuation of computing performance improvement despite the slowed-down physical device scaling. One new frontier in this field focuses on Artificial Intelligence (AI) hardware. While functionality of AI hardware still remains the main focus, testability and dependability of these new architectures need to be addressed before the mainstream adoption. This survey paper covers the state-of-the-art in research and development of dependability and testability solutions for AI hardware including digital or analog implementations of Artificial Neural Networks (ANNs) and Spiking Neural Networks (SNNs), used in accelerators and neuromorphic designs. Trends, challenges and perspectives are also discussed in this paper.

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Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

“…RTL-level, microarchitectural-level, gate-level, and transistor-level fault injection takes into consideration the Fig. 12: ML-based method for criticality assessment [98].…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

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