Fully Parallel Stochastic LDPC Decoders

Abstract

Abstract-Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array ( Index Terms-Field programmable gate arrays (FPGAs), iterative decoding, low-density parity-check (LDPC) codes , stochastic decoding.

A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes

“…A decoding cycle corresponds to 1 bit being processed by the variable nodes, sent to the check nodes and sent back to the variable nodes. We note that a decoding cycle in a stochastic decoding algorithm is not equivalent to an iteration in a message passing algorithm such as SPA [7]. The code used for the simulations is a (6, 32)-regular RS-based LDPC code of size 2048 and rate 0.84, which has a girth of 6.…”

“…The results reported in [7] reduce the upper limit to 700 iterations, but the performance is approximately 0.5 dB away from 32-iterations floating-point SPA (at a BER of 10 −8 ). A very attractive aspect of stochastic decoders is that they only require two wires per bidirectional edge of the Tanner graph, therefore bringing the circuit's interconnect to its simplest expression.…”

“…The latter is preferred because many stochastic output bits can be generated from the same random number. In fact, it has been reported in [7] that only a small number of independent random number generators (RNGs) are needed in a complete stochastic decoder.…”

“…In [6], the authors improved the stochastic decoding algorithm in order to achieve good decoding performance on larger codes. The decoder was refined again in [7], which also presented FPGA implementation results for practical codes.…”

“…The check nodes for SPA and min-sum algorithm (MSA) decoders of this code have high-area implementations, even for bit-serial MSA decoders [8], [9]. In addition to the low complexity, another important advantage of stochastic decoders is the ability to add pipeline stages on some or all edges of the interleaver without affecting the error-correction performance [7]. This allows higher clock rates, and for an ASIC implementation can facilitate the layout and routing.…”