Fully-isolated silicon RF LDMOS for high-efficiency mobile power conversion and RF amplification

Zierak, M.; Feilchenfeld, N.; Li, Chaojiang; Letavic, T.

doi:10.1109/ispsd.2015.7123458

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…EDMOS) are the most suitable for this purpose. Although 5V-LDMOS transistors are developed and offered in most advanced processesranging from bulk to FDSOI (15)(16)(17)(18)(19) and from planar to FinFET (9, 20-21)their RF performance is often quite limited. As well-known in RF circuit design, for most implementations, the cutoff frequency fT of the device must be at least 5x higher than the operating frequency (2)(3).…”

Section: Rf High-voltage Active Devices In Fdsoimentioning

confidence: 99%

(Keynote) Fully-Depleted SOI Technology for High-Power RF Applications

Dinh

2020

ECS Trans.

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Section: Rf High-voltage Active Devices In Fdsoimentioning

confidence: 99%

(Keynote) Fully-Depleted SOI Technology for High-Power RF Applications

Dinh

2020

ECS Trans.

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“…According to our literature review, our device has overall a better FoM, higher g m at high gate voltages, an acceptable I off , and high f T , Thus, we expect better performance in power amplifiers (PAs) in the targeted IoT ASICs similar in nature to. 14,15 According to, 16 the power consumption of a PA is of great importance. Achieving an efficient yet stable PA requires an adequate selection of the class, circuit solutions, an efficient process, and mask layout.…”

Section: Introductionmentioning

confidence: 99%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (R ON,SP ) is 94 mΩmm 2 , and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (g m ) at high gate voltages, with acceptable off-state leakage current (I off ), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (f MAX ) and cutoff frequency (f T ) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

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