Fully integrated dual-band VCOs with power controlled by body voltage in 130 nm CMOS/SOI for multi-standard applications

Abstract

In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were -89 and -93 dBc/Hz at 5.2 and 3.6 GHz respectively.

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

“…However, the tail current transistor, MT in Figure 21, is one of the biggest noise contributors of this structure [19]. Different techniques to reduce this noise have been proposed, such as sinusoidal tail current shaping [20], tail current flicker noise reduction by complementary switched biasing [21], sinusoidal shaping of the ISF [22], novel tail current noise second harmonic filtering [23], … A significant and interesting contribution was proposed in 2007 [24] using SOI technology. In fact, the technology was PD (partially depleted) SOI, which allows to suppress the tail current transistor.…”

“…. A significant and interesting contribution was proposed in 2007 [24] using SOI technology. In fact, the technology was PD (partially depleted) SOI, which allows to suppress the tail current transistor.…”