Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter

Novof, I.; Austin, J.; Chmela, R.; Frank, T.; Kelkar, Ramesh B.; Short, K. T.; Strayer, D. M.; Styduhar, Mark; Wyatt, S.

doi:10.1109/4.475714

Cited by 74 publications

(11 citation statements)

References 5 publications

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“…Note that the simulated and calculated eye diagrams are virtually identical, meaning the error in the first-order Taylor series approximation is acceptable. 7 We now present simulation results that demonstrate noise margin degradation due to receiver clock jitter. The simulated opening of the eye diagram with 30 k data bits 8 and 5 p/s rms jitter is shown in Fig.…”

Section: Behavioral Simulationsmentioning

confidence: 95%

“…where is the worst-case/peak ISI distortion data sequence derived using (7). A specific example of this is illustrated later in Section VI.…”

Section: A Peak Distortion Analysismentioning

confidence: 99%

“…Intuitively, we expect the transmit jitter to be filtered by the channel in some fashion and the second term in (13) reinforces our intuition. Due to the modulation of by the jitter sequence , we can evaluate the peak distortion due to transmitter clock jitter, i.e., the peak distortion of the second term , by (14) where is the worst-case/peak ISI distortion data sequence derived using (7). It is interesting to note that the peak distortion due to transmitter clock jitter noise can be potentially greater than that of receiver sampling jitter for the similar amount of receiver and transmitter jitter.…”

Section: A Peak Distortion Analysismentioning

confidence: 99%

“…Jitter is incorporated by randomly varying the optimal sampling point. 7 First-order Taylor series approximation can be directly validated by comparing the approximate step response with actual step response. However, it is not clear how this error translates to the error in the eye diagram.…”

Section: Behavioral Simulationsmentioning

confidence: 99%

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Analysis of PLL clock jitter in high-speed serial links

Hanumolu¹,

Casper²,

Mooney³

et al. 2003

IEEE Trans. Circuits Syst. II

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We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.

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Section: Behavioral Simulationsmentioning

confidence: 95%

“…where is the worst-case/peak ISI distortion data sequence derived using (7). A specific example of this is illustrated later in Section VI.…”

Section: A Peak Distortion Analysismentioning

confidence: 99%

Section: A Peak Distortion Analysismentioning

confidence: 99%

Section: Behavioral Simulationsmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of PLL clock jitter in high-speed serial links

Hanumolu¹,

Casper²,

Mooney³

et al. 2003

IEEE Trans. Circuits Syst. II

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“…One most commonly used way is to use voltage-controlled oscillator (VCO) with phase-locked loop (PLL) [1]- [3]. But this type of clock has some inherent problems [4], [5].…”

Section: Introductionmentioning

confidence: 99%

An on-chip low power clock multiplier unit in 0.25 micron technology

Setu

Raju

Weerasekera³

Canadian Conference on Electrical and Computer Engineering, 2005.

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Other Building Blocks of PLL

CMOS PLL Synthesizers: Analysis and Design

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This chapter covers the design of PLL synthesizer blocks of the experimental PLL prototype other than the prescaler and loop filter. General analysis and design techniques of each building block are overviewed. The analysis methods of the VCO phase noise are summarized. A complete analysis of the reference spur is also made in this chapter. VCOBasically, there are two types of on-chip VCO's for high frequency PLL's: the ring oscillator and the LC-tuned oscillator. The ring oscillator consists of a number of delay stages. It usually takes less area and has a large tuning range. The LC oscillator often takes more chip area due to spiral inductors and has a smaller tuning range, but it can run at a much higher frequency and generally its phase noise is better. Varactor A. Diode varactorThe reverse-biased diode, which is usually made of p-diffusion in n-well can be used as a varactor. It is a lateral device consisting of p'-n--n' diffusion sequence. Since the n-well has a high resistivity (at least hundreds of Qlsquare), the parasitic resistance introduced by the diode varactor is of a big concern. Efforts in optimizing the layout have been made in the literature to reduce the parasitic resistance [5]- [7]. Also caution should be used to keep the diode varactor working in reverse-biased mode in the VCO tuning range and oscillating range. B. PMOS varactorThe well-known C-V characteristic of MOS transistor can be employed as a varactor for LC-VCO. The gate-to-substrate capacitance of a MOS transistor, C,,, , varies with the voltage drop between substrate and gate, V, , . Usually, the C-V characteristic of a MOS transistor is for a very small v,, signal superimposed on bias voltage V, , . If the LC-VCO, the signal v,, is large and the instantaneous value of C,,, changes through the OTHER BUILDING BLOCKS OF PLLoscillating period, nut the average value of C,,, still varies with control voltage V, , .For a p-sub, n-well CMOS process, the MOS varactor can be two PMOS sharing the same n-well. The bias of the n-well, which is the substrate of the two PMOS transistors, is used as the frequency control node of the VCO. To reduce the parasitic resistance of MOS varactor, minimum channel length should be used to minimize the channel resistance, and the multi-finger layout is used to reduce the resistance of the poly gate. The Q of a MOS varactor is roughly proportional to the reverse of channel length and the typical Q value is between 10 and 100 [7]-[lo]. C. Inversion-mode PMOS varactor (I-MOS)Since the MOS transistor has a non-monotonic C-V characteristic, the VCO with PMOS varactors shows a non-monotonic tuning characteristic. One way to obtain a quasi-monotonic tuning characteristic MOS varactor is by ensuring that the transistor does not enter the accumulation region for a very wide range of values of V,. This is accomplished by connecting the substrate to the highest DC voltage, i.e., VDD . D. Accumulation-mode PMOS varactor (A-MOS)A more attractive alternative is the use of the PMOS device in the depletion and accumulation...

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Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter

Cited by 74 publications

References 5 publications

Analysis of PLL clock jitter in high-speed serial links

Analysis of PLL clock jitter in high-speed serial links

An on-chip low power clock multiplier unit in 0.25 micron technology

Other Building Blocks of PLL

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