Fully hardware based WFQ architecture for high-speed QoS packet scheduling

McLaughlin, Kieran; Burns, D. C.; Toal, C.; McKillen, C.; Sezer, Sakir

doi:10.1016/j.vlsi.2011.01.001

Cited by 11 publications

(6 citation statements)

References 37 publications

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“…Afek [26] proposed a PQ using TCAM/SRAM. This author showed the efficiency of the proposed solution and its advantages over other ASIC designs [20], [22], [23], but its overall rate degrades almost linearly with larger queue size while targeting 100 Gb/s line rate. Also, Afek presented an estimation of performance with no actual implementation.…”

Section: Related Workmentioning

confidence: 92%

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HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices

2019

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In this paper, we present a fast hybrid priority queue architecture intended for scheduling and prioritizing packets in a network data plane. Due to increasing traffic and tight requirements of high-speed networking devices, a high capacity priority queue, with constant latency and guaranteed performance is needed. We aim at reducing latency to best support the upcoming 5G wireless standards. The proposed hybrid priority queuing system (HPQS) enables pipelined queue operations with almost constant time complexity in practice. The proposed architecture is implemented in C++, and is synthesized with the Vivado High-Level Synthesis (HLS) tool. Two configurations are proposed. The first one is intended for scheduling with a multi-queuing system for which implementation results of 64 up to 512 independent queues are reported. The second configuration is intended for large capacity priority queues, that are placed and routed on a ZC706 board and a XCVU440-FLGB2377-3-E Xilinx FPGA supporting a total capacity of 1/2 million packet tags. The reported results are compared across a range of priority queue depths and performance metrics with existing approaches. The proposed HPQS supports links operating at 40 Gb/s. INDEX TERMS Priority queue, networking devices, high-level synthesis, field-programmable gate array (FPGA).

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Section: Related Workmentioning

confidence: 92%

“…McLaughlin [22], [23] proposed a packet sorting circuit based on a lookup tree (a trie). This architecture is composed of three main parts: the tree that performs the lookup function with 8 Ki capacity, the translation table which connects the tree to the third part, the tag storage memory.…”

Section: Related Workmentioning

confidence: 99%

HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices

2019

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“…McLaughlin [11] demonstrated an efficient hardware sorting circuit and subsequently achieved fully implementation [12] of the WFQ algorithm on FPGA. During the sorting process, a linked list structure is employed to store the sorted tags, while a lookup tree and a translation table are utilized to determine the position of new tags within the linked list.…”

Section: Related Work 21 Tag Sorting Circuitmentioning

confidence: 99%

QGWFQS: A Queue-Group-Based Weight Fair Queueing Scheduler on FPGA

Guo,

Song

et al. 2023

Micromachines

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Weight Fair Queuing is an ideal scheduling algorithm to guarantee the bandwidth of different queues according to their configured Weights when the switching nodes of the network are congested. Many of the switching nodes based on FPGA in the current network support four physical ports or hundreds of virtual ports. Massive logic and storage resources would be consumed if each port implemented a WFQ scheduler. This paper proposes a Queue-Group-Based WFQ Scheduler (QGWFQS), which can support WFQ scheduling across multiple ports through the reuse of tag calculation and encoding circuits. We also propose a novel finish tag calculation algorithm to accommodate the variation in the link rate of each port. The remainder of integer division is also taken into account, which makes the bandwidth allocation fairer. Experimental results show that the proposed scheduler supports up to 512 ports, with 32 queues allocated on each individual port. The scheduler has the capability to operate at 200 MHz and the total scheduling capacity reaches 200 Mpps.

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“…As resources are getting scarcer in modern networks, optimum resource allocation and congestion control have become a challenging issue [1]. Since stations in the ring structure utilize a shared medium, so this problem is more and more intricate.…”

Section: Introductionmentioning

confidence: 99%

A New Adaptive Prioritization and Fail-Over Mechanism for Ring Network Adapter

2020

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This paper presents a new adaptive prioritization and fail-over mechanism for ring network adapters (RNA). Owing to the use of a shared medium in the structure of ring networks, management of network resources is very important and cannot completely be fulfilled by fixed priority strategies. An adaptive prioritization mechanism for efficient utilization of network resources is proposed in this paper. Hop-Count and the distance between source and destination are the key parameters that are included in the priority assignment procedure. Unlike the conventional ones, the arrived traffic is not put blindly into the queues thanks to the awareness of stations form status of each other. The newly introduced fail-over mechanism is based on the Power over Ethernet concept. Each station monitors the heartbeat of its neighbors and tries to keep them alive by providing their minimum required electrical power whenever a fault occurs. By doing so, not only single failure but also any successive double failure scenarios cannot disrupt data path continuity. Several simulations are carried out to assess the behavior and performance of the proposed methods in OPNET Modeler. Moreover, a high-speed USB test board is designed using Xilinx-Spartan6-lx9 FPGA to experimentally verify the performance of the proposed mechanisms. INDEX TERMS Ring network, weighted fair queuing, node failure, fail-over mechanism, power over Ethernet.

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Fully hardware based WFQ architecture for high-speed QoS packet scheduling

Cited by 11 publications

References 37 publications

HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices

HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices

QGWFQS: A Queue-Group-Based Weight Fair Queueing Scheduler on FPGA

A New Adaptive Prioritization and Fail-Over Mechanism for Ring Network Adapter

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