Fully digital neural network implementation based on pulse density modulation

Tomberg, J.; Ritoniemi, T.; Kaski, Kimmo; Tenhunen, Hannu

doi:10.1109/cicc.1989.56744

Cited by 17 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…3.1, weight matrices can be changed at every CPWM clock cycle, during the idle phase. Preliminary results indicate that 100ns D A converters with a size of 350 250m 2 and about 11mW power dissipation per converter are feasible. For an array o f 3 2 c o n v erters, these gures correspond to an update rate of about 10 8 weights s, with a total power dissipation of about 350mW.…”

Section: Large Networkmentioning

confidence: 99%

“…Although most practical applications of Arti cial Neural Systems ANS are still carried out using software simulators, more and more designers are developing speci c VLSI circuits using various techniques, ranging from fully digital to fully analog and even optical ones 5 . Because of the advantages they provide, Pulse Streams" PS are gaining acceptance in the eld of hardware implementations of ANS 1,2,3,4,5,8,13 . PS are a class of modulations using quasi periodic" binary signals; information is contained in waveform timing and not in the amplitude. In Neural Systems, PS are primarily used to encode input i i and output y j activation signals both will be named i and synaptic weights w j i .…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Using Coherent Pulse Width and Edge Modulations in Artificial Neural Systems

Reyneri

Chiaberge

Corso

1993

Int. J. Neur. Syst.

View full text Add to dashboard Cite

This paper describes an existing silicon implementation of an artificial neural system based on coherent pulse width and edge modulation techniques. A chip set with different neural functions has been conceived, manufactured and tested. Neural circuits have been optimized for lowest computation energy and highest reconfigurability. The main device is a 32 × 32 synaptic array consuming 10 mW of power at 140 MCPS. Synapsis size is about 7.200 μ m 2 using a standard 1.5 μm CMOS technology. The problem of interfacing robotic sensors and actuators is addressed: voltage, current and resistance-based sensors are considered for the measurement of physical quantities such as temperature, pressure, strain, etc. Low resolution imaging sensors for robotic vision are also considered.

show abstract

Section: Large Networkmentioning

confidence: 99%