Fully-Depleted Silicon-on-Insulator (FDSOI) Based Complementary Phototransistors for In-Sensor Vector-Matrix Multiplication

Abstract

Two type CMOS-compatible complementary phototransistors (CPTs) with NMOS or PMOS transistor are proposed in this work for in-sensor vector-matrix multiplication (VMM). The CPT is fabricated by the 22nm FDSOI process technology and composed of a MOSFET with a p-doped well under the buried oxide (BOX). The well serves for photoelectron generation and affects the on-state current of the MOSFET by the photoelectrons. The bidirectional and tunable photoresponsivity characteristics as well as the optical-electrical signed multiplication operation (average error <2.5%) are experimentally demonstrated in the pair of CPTs. The in-sensor VMM is verified by typical artificial neural networks using the CPT array as the imageinput layer. Simulated results show slight inference accuracy losses (<1%) in LeNet3 for MNIST and VGG11/VGG16 for CIFAR-10 recognition.

Gate-controlled gain tuning of fully depleted silicon-on-insulator-based 1 T pixel for in-sensor white balance

“…8) In order to reduce data transmission and improve processing efficiency, in-sensor computing [9][10][11] has been developed as a promising paradigm for intelligent image sensors to take advantage of the inherent data locality by shifting ahead the computing functions into sensor terminals. [12][13][14][15] In the conventional image processing pipeline, the image signal processor (ISP) 16) further processes the light information captured by pixels to enhance the image quality in the approach of various computational functions such as demosaicing and flat-field correction. 17,18) It is typically integrated as a digital processor, consuming considerable computing resources.…”

“…In this study, we propose a novel pixel-level gain-tuning method utilizing the fully depleted silicon-on-insulator (FDSOI) one-transistor (1 T) pixel to realize in-sensor WB. The FDSOI-based 1 T pixel sensor 15,[25][26][27][28][29] has been extensively studied in the past few years, and is becoming an outstanding candidate due to its potential of higher resolution and excellent CMOS compatibility. In this work, the 1 T pixel 15,30,31) is composed of an n-type nMOSFET for signal readout and a p-well under the buried oxide (BOX) for sensing.…”

“…The FDSOI-based 1 T pixel sensor 15,[25][26][27][28][29] has been extensively studied in the past few years, and is becoming an outstanding candidate due to its potential of higher resolution and excellent CMOS compatibility. In this work, the 1 T pixel 15,30,31) is composed of an n-type nMOSFET for signal readout and a p-well under the buried oxide (BOX) for sensing. According to the transistor transfer characteristics, the 1 T pixel output gain can be modulated by the MOSFET gate at different voltage levels.…”

A compact model for the well-depleted 1-T pixel sensor based on silicon-on-insulator technology

“…14) The silicon-on-insulator (SOI) based 1-T pixel sensor is an outstanding candidate based on its low-operating voltage and excellent CMOS compatibility. It is generally composed of a transistor on the buried oxide (BOX) and a doping well [15][16][17][18] or photodiode 19,20) under the BOX. The light is converted into photoelectrons in the depleted well or photodiode and affects the transistor current due to the backgate modulation.…”

“…Moreover, the SOI-based 1-T pixel sensor has also shown a bidirectional photoresponse by altering the N-or P-type transistor, which is suitable for in-sensor computing. 15,21) In order to efficiently evaluate the performance of the SOI 1-T pixel sensor in the array scale for imaging and in-sensor computing applications, compact models for photoresponse are indispensable. Most compact models of typical SOI MOSFET, such as Leti-UTSOI 22,23) and BSIM-IMG 24,25) do not involve the generation and influence of photoelectrons, and therefore cannot evaluate the photoresponse.…”