2020
DOI: 10.1109/ted.2020.2985639
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Fully Depleted MAPS in 110-nm CMOS Process With 100–300-μm Active Substrate

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Cited by 30 publications
(20 citation statements)
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“…TCAD simulations were also performed to estimate the voltage range that needs to be applied to the backside contact for the correct operation of the sensors. As reported in [ 16 ], this operating voltage should be larger than the one associated to full depletion, but small enough to avoid an excessive punch through current flow.…”
Section: Tcad Simulationsmentioning
confidence: 98%
See 1 more Smart Citation
“…TCAD simulations were also performed to estimate the voltage range that needs to be applied to the backside contact for the correct operation of the sensors. As reported in [ 16 ], this operating voltage should be larger than the one associated to full depletion, but small enough to avoid an excessive punch through current flow.…”
Section: Tcad Simulationsmentioning
confidence: 98%
“…In the first production run, both active pixel arrays with embedded electronics and passive test structures, designed to extract the device characteristic parameters and to characterize the sensor backside diodes, were included. Simulation and characterization results on active pixel arrays and test structures fabricated with this process were reported in [ 16 ]. Since a high voltage bias has to be applied to the backside junction to reach full depletion in thick silicon substrates, dedicated termination structures were designed to avoid an early breakdown of the backside junction.…”
Section: Introductionmentioning
confidence: 99%
“…The ARCADIA project and its precursor, SEED (Sensor with Embedded Electronics Development), designed an innovative sensor concept [ 37 , 38 ] based on a modified 110 nm CMOS process developed in collaboration with LFoundry and compatible with their standard 110 nm CMOS process. Up to 6 metal layers can be stacked on top of the sensor, for a total metal and insulator thickness of about 4–5 m. The ARCADIA collaboration is developing a scalable event-driven readout architecture to cover detection surfaces of O(cm ) while maintaining ultra-low power consumption.…”
Section: The Arcadia Sensor Conceptmentioning
confidence: 99%
“…The feasibility of this sensor concept and approach to Fully Depleted monolithic CMOS sensors was proven in the framework of the SEED project [ 37 , 38 ], and the design activities described in this article have as a starting point the experimental and simulation work performed in that project. The main constraint on the design was to reduce to the minimum the modifications to the foundry’s standard fabrication process, in order to guarantee easy portability to different commercial fabrication processes.…”
Section: The Arcadia Sensor Conceptmentioning
confidence: 99%
“…A more compact circuit, such as the one used in the ALPIDE chip [12], has also been designed and will be tested in a dedicated prototype. A more detailed description of the processing is provided in [16].…”
Section: Introductionmentioning
confidence: 99%