Full-wave characterization of the crosstalk reduction effect of an additional grounded track introduced between two printed circuit tracks

Coetzee, Jacob; Joubert, J.

doi:10.1109/81.508174

Cited by 10 publications

(3 citation statements)

References 11 publications

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“…The crosstalk can be reduced by introducing additional ground track between the interfering lines (Kim et al , 2005; Suntives et al , 2006; Kim and Park, 2006). The full wave spectral domain analysis for crosstalk reduction has been discussed in Coelzec and Joubert (1996).…”

Section: Interconnectsmentioning

confidence: 99%

VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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PurposeThe purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approachIn the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.FindingsThe effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.Originality/valueThis paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

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Section: Interconnectsmentioning

confidence: 99%

VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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“…These interconnect structures differ in their electrical characteristics from standard microstrip lines [1]. While ground plane aperture (GPA) is used in the design of microstrip filters [2][3][4], couplers [5,6] and split rings, the adjacent ground tracks are common in crosstalk immune electronic systems [7][8][9][10][11][12]. In this work, we propose a new set of analytical expressions for characteristic impedance of the interconnect structures shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Empirical expressions for characteristic impedance of modified microstrip-like interconnections

Sharma

Chakravarty

Bhattacharyya

2010

AEU - International Journal of Electronics and Communications

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“…Ground tracks adjacent to high-speed interconnections are often used for reduction of crosstalk in a variety routing topologies [1,2] and high-speed mixed signal systems [3][4][5][6]. While full-wave spectral domain analysis for crosstalk reduction using additional ground tracks has been discussed in detail [7]; the effect of such ground tracks on the propagation delay of the interconnect line itself is usually lost sight of. From the point of view of multichip system design, a parametric study of the effect of these grounds tracks on the delay prediction in high-speed interconnects is imperative.…”

Section: Introductionmentioning

confidence: 99%

Transient Analysis of Microstrip Â Like Interconnections Guarded by Ground Tracks

Sharma¹,

Chakravarty²,

Bhattacharyya³

2008

PIER

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Abstract-Guarded ground tracks are extensively used in high density routing for mitigation of crosstalk. However, these ground tracks can influence the electrical properties of the interconnect line also. We present a novel analytical model for extraction of line parameters of high-speed interconnect lines guarded by ground tracks. Based on the proposed model, transient response of such interconnect structures is presented. It is seen ground tracks can significantly affect the time-domain response of the interconnect lines. The computed interconnect circuit parameters are compared with finite-difference time-domain simulations. The proposed model can be practically used for time-domain analysis of microstrip lines also. The results obtained would be useful in design of high-speed interconnections for MCM, RF and MIC related applications.

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Full-wave characterization of the crosstalk reduction effect of an additional grounded track introduced between two printed circuit tracks

Cited by 10 publications

References 11 publications

VLSI interconnects and their testing: prospects and challenges ahead

VLSI interconnects and their testing: prospects and challenges ahead

Empirical expressions for characteristic impedance of modified microstrip-like interconnections

Transient Analysis of Microstrip Â Like Interconnections Guarded by Ground Tracks

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Full-wave characterization of the crosstalk reduction effect of an additional grounded track introduced between two printed circuit tracks

Cited by 10 publications

References 11 publications

VLSI interconnects and their testing: prospects and challenges ahead

VLSI interconnects and their testing: prospects and challenges ahead

Empirical expressions for characteristic impedance of modified microstrip-like interconnections

Transient Analysis of Microstrip Â Like Interconnections Guarded by Ground Tracks

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Product

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Transient Analysis of Microstrip Â Like Interconnections Guarded by Ground Tracks