Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration

Butko, Anastasiia; Bruguier, Florent; Gamatié, Abdoulaye; Sassatelli, Gilles; Novo, David; Torres, Lionel; Robert, Michel

doi:10.1109/mcsoc.2016.20

Cited by 36 publications

(35 citation statements)

References 16 publications

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“…The power model accounts for core active, wait-for-memory (WFM) and static energy (in J/cycle), and the LLC read and write energy (in J/access). We did not use gem5 power model, as proposed by Reddy et al (2017) or McPAT power model, as proposed by (Butko et al 2016), as they both are for ARMv7 32-bit ISA, whereas we are using ARMv8 64-bit cores. • Hardware Architecture: As a starting point for our exploration, we model the ARM JUNO platform in gem5-X, with 4 OoO cores instead of 2 to have a fair comparison between different architectures and core types, each with 4 cores as a starting point.…”

Section: Methodsmentioning

confidence: 99%

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Qureshi

Simon

Zapater

et al. 2019

2019 Spring Simulation Conference (SpringSim)

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The rapid expansion of online-based services requires novel energy and performance efficient architectures to meet power and latency constraints. Fast architectural exploration has become a key enabler in the proposal of architectural innovation. In this paper, we present gem5-X, a gem5-based system level simulation framework, and a methodology to optimize many-core systems for performance and power. As real-life case studies of many-core server workloads, we use real-time video transcoding and image classification using convolutional neural networks (CNNs). Gem5-X allows us to identify bottlenecks and evaluate the potential benefits of architectural extensions such as in-cache computing and 3D stacked High Bandwidth Memory. For real-time video transcoding, we achieve 15% speed-up using in-order cores with in-cache computing when compared to a baseline in-order system and 76% energy savings when compared to an Out-of-Order system. When using HBM, we further accelerate real-time transcoding and CNNs by up to 7% and 8% respectively.

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Section: Methodsmentioning

confidence: 99%

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Qureshi

Simon

Zapater

et al. 2019

2019 Spring Simulation Conference (SpringSim)

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“…We used the gem5 [10] cycle-accurate simulator to estimate the performance impact both on the main CPU by modeling an x86 system, and on the co-processor by modeling an ARM Cortex A5. Butko et al [15] evaluated that gem5 gave a performance prediction with a 20% error on average.…”

Section: Methodsmentioning

confidence: 99%

Co-processor-based Behavior Monitoring

Chevalier

Villatel

Plaquin

et al. 2017

Proceedings of the 33rd Annual Computer Security Applications Conference

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Highly privileged software, such as firmware, is an attractive target for attackers. Thus, BIOS vendors use cryptographic signatures to ensure firmware integrity at boot time. Nevertheless, such protection does not prevent an attacker from exploiting vulnerabilities at runtime. To detect such attacks, we propose an event-based behavior monitoring approach that relies on an isolated co-processor. We instrument the code executed on the main CPU to send information about its behavior to the monitor. This information helps to resolve the semantic gap issue. Our approach does not depend on a specific model of the behavior nor on a specific target. We apply this approach to detect attacks targeting the System Management Mode (SMM), a highly privileged x86 execution mode executing firmware code at runtime. We model the behavior of SMM using invariants of its control-flow and relevant CPU registers (CR3 and SMBASE). We instrument two open-source firmware implementations: EDK II and coreboot. We evaluate the ability of our approach to detect state-of-the-art attacks and its runtime execution overhead by simulating an x86 system coupled with an ARM Cortex A5 co-processor. The results show that our solution detects intrusions from the state of the art, without any false positives, while remaining acceptable in terms of performance overhead in the context of the SMM (i.e., less than the 150 µs threshold defined by Intel).

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“…Its full-system simulation mode runs unmodified operating systems. It has been used for the accurate modeling and evaluation of modern multicore architectures, such as ARM big.LITTLE [13]. NVMain [12] is an architectural-level simulator that enables to model main memory design with both DRAM and emerging non-volatile memory technologies.…”

Section: System Level Analysismentioning

confidence: 99%

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Perumkunnil

Rock

Hartmann

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multicore architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration

Cited by 36 publications

References 16 publications

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Co-processor-based Behavior Monitoring

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

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