Full-System Simulation from Embedded to High-Performance Systems

Engblom, Jakob; Aarno, Daniel; Werner, Bengt

doi:10.1007/978-1-4419-6175-4_3

Cited by 20 publications

(14 citation statements)

References 7 publications

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“…We implemented the proposed cache partitioning scheme using the Simics full-system simulator [8] and GEMS executiondriven multiprocessor simulation framework [9]. Our system comprises of a quad-core processor where the cores have private L1 caches and a shared last level L2 cache.…”

Section: Experimental Methodology and Resultsmentioning

confidence: 99%

Variation Aware Cache Partitioning for Multithreaded Programs

Kozhikkottu¹,

Pan²,

Pai³

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Multithreaded programs are commonly written and optimized for homogeneous multi-core processors assuming equal performance from all the cores. This assumption greatly simplifies the partitioning and balancing of an application's workload across threads; however, it no longer holds when the frequencies of the cores differ due to within-die variations, leading to a degradation in performance. We observe that, in addition to the frequency of the core that it executes on, the performance of a thread is also dependent on the share of shared system resources, such as last-level cache, that it receives. We propose variation-aware cache partitioning as an approach to redress the variation-induced imbalance in the execution times of threads, thereby improving the performance of multi-threaded programs. We discuss the challenges involved in realizing our proposal, including synchronization (e.g., barriers) across threads, which results in faster threads being limited by slower threads, the complex and non-linear relationship between a thread's performance and the cache capacity allocated to it, and the fact that different program phases, can respond quite differently to varying cache capacity. We propose a runtime scheme to perform spatio-temporal cache partitioning while considering both chip characteristics (frequency variations) and program characteristics. We evaluate the proposed technique by applying it to an ensemble of variation-impacted multi-cores executing multi-threaded programs from the PAR-SEC and SPEC-OMP suites, and demonstrate that it results in an average performance improvement of 15% by mitigating the impact of frequency variations.

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Section: Experimental Methodology and Resultsmentioning

confidence: 99%

Variation Aware Cache Partitioning for Multithreaded Programs

Kozhikkottu¹,

Pan²,

Pai³

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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show abstract

“…Next, P1 spawns a child process P2 using fork. While P2 is sleeping (line 6), P1 renames "file1" to "file2" and waits for P2 to exit (lines [16][17]. After P2 wakes up, it writes a string into "file2" (lines 7-8).…”

Section: Real-world Examples Of System-level Racesmentioning

confidence: 99%

An automated framework to support testing for process‐level race conditions

Srisa-an

Rothermel

2017

Software Testing Verif & Rel

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Summary Race conditions are difficult to detect because they usually occur only under specific execution interleavings. Numerous program analysis and testing techniques have been proposed to detect race conditions between threads on single applications. However, most of these techniques neglect races that occur at the process level due to complex system event interactions. This article presents a framework, SIMEXPLORER, that allows engineers to effectively test for process‐level race conditions. SIMEXPLORER first uses dynamic analysis techniques to observe system execution, identify program locations of interest, and report faults related to oracles. Next, it uses virtualization to achieve the fine‐grained controllability needed to exercise event interleavings that are likely to expose races. We evaluated the effectiveness of SIMEXPLORER on 24 real‐world applications containing both known and unknown process‐level race conditions. Our results show that SIMEXPLORER is effective at detecting these race conditions, while incurring an overhead that is acceptable given its effectiveness improvements.

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“…GEMS uses the Simics full-system simulator as its functional simulation engine [8]. The system modeled is a single-chip multiprocessor with one highly-associative lastlevel shared L2 cache with private L1 caches.…”

Section: Evaluation Frameworkmentioning

confidence: 99%

Imbalanced cache partitioning for balanced data-parallel programs

Pan

Pai

2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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This paper investigates partitioning the ways of a shared last-level cache among the threads of a symmetric dataparallel application running on a chip-multiprocessor. Unlike prior work on way-partitioning for unrelated threads in a multiprogramming workload, the domain of multithreaded programs requires both throughput and fairness. Additionally, our workloads show no obvious thread differences to exploit: program threads see nearly identical IPC and data reuse as they progress (as expected for a well-written loadbalanced data-parallel program).Despite the balance and symmetry among threads, this paper shows that a balanced partitioning of cache ways between threads is suboptimal. Instead, this paper proposes a strategy of temporarily imbalancing the partitions between different threads to improve cache utilization by adapting to the locality behavior of the threads as captured by dynamic set-specific reuse-distance (SSRD). Cumulative SSRD histograms have knees that correspond to different important working sets; thus, cache ways can be taken away from a thread with only minimal performance impact if that thread is currently operating far from a knee. Those ways can then be given to a single "preferred" thread to push it over the next knee. The preferred thread is chosen in a round-robin fashion to ensure balanced progress over the execution. The algorithm also effectively handles scenarios where an unpartitioned cache might outperform any sort of explicit partitioning. This dynamic partition imbalance algorithm allows up to 44% reduction in execution time and 91% reduction in misses over an unpartitioned shared cache for 9 benchmarks from the PARSEC-2.0 and SPEC OMP suites.

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Full-System Simulation from Embedded to High-Performance Systems

Cited by 20 publications

References 7 publications

Variation Aware Cache Partitioning for Multithreaded Programs

Variation Aware Cache Partitioning for Multithreaded Programs

An automated framework to support testing for process‐level race conditions

Imbalanced cache partitioning for balanced data-parallel programs

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