2019
DOI: 10.1109/ted.2019.2922696
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Full-Swing, High-Gain Inverters Based on ZnSnO JFETs and MESFETs

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Cited by 13 publications
(12 citation statements)
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“…In the on-state of the driving transistor, the output voltage is still 0.5 V rather than the expected ground potential of 0 V. This can be attributed to the low threshold voltage, causing the pull-up transistor to increasingly operate in the saturation regime at higher I D . In this case, the pgm slightly decreases to 75, whereas V UC remains 0.5 V at an operating voltage of 5 V. Previously reported ZTO-based SDFL inverters, comprising MESFETs, exhibited a remarkable pgm of 294 at V DD = 5 V. [16] This significant discrepancy in maximum gain can be attributed to the voltage dependency of the saturation current of the pull-up transistors and driving transistor at V G = 0 V for our devices (see Figure 2b). Fullswing ZTO-based inverters with sufficient level shift have previously been achieved using MESFETs and JFETs with threshold voltages approaching 0 V. [16] However, a decreased logic swing does not affect the cascadability of SDFL inverters as long as the total level shift V shift is sufficiently high.…”
Section: Resultsmentioning
confidence: 70%
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“…In the on-state of the driving transistor, the output voltage is still 0.5 V rather than the expected ground potential of 0 V. This can be attributed to the low threshold voltage, causing the pull-up transistor to increasingly operate in the saturation regime at higher I D . In this case, the pgm slightly decreases to 75, whereas V UC remains 0.5 V at an operating voltage of 5 V. Previously reported ZTO-based SDFL inverters, comprising MESFETs, exhibited a remarkable pgm of 294 at V DD = 5 V. [16] This significant discrepancy in maximum gain can be attributed to the voltage dependency of the saturation current of the pull-up transistors and driving transistor at V G = 0 V for our devices (see Figure 2b). Fullswing ZTO-based inverters with sufficient level shift have previously been achieved using MESFETs and JFETs with threshold voltages approaching 0 V. [16] However, a decreased logic swing does not affect the cascadability of SDFL inverters as long as the total level shift V shift is sufficiently high.…”
Section: Resultsmentioning
confidence: 70%
“…An essential step toward the realization of ring oscillators are investigations on the cascadability of the respective inverters. Here, we employ the SDFL approach that has already been successfully demonstrated for ZTO‐based inverters comprising depletion‐type MESFETs and JFETs . To achieve compatible output and input voltage levels, our SDFL circuits implement PtO x / i ‐ZTO/ZTO Schottky barrier diodes for shifting of the output voltage by means of a voltage drop across the diodes in order to switch a subsequent inverter.…”
Section: Resultsmentioning
confidence: 99%
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“…Since previous investigations on ZTO-based FETs indicated the formation of a highly conductive ZTO layer close to the substrate, inhibiting sufficient depletion of the channel, the sputtering process was ignited in an oxygen-rich atmosphere of 25/30 sccm O 2 /Ar. [18,19] Subsequently, a conductive ZTO channel layer has been deposited on top of the intrinsic buffer layer. Source and drain contacts consist of ZnO : 4 wt% Ga 2 O 3 (GZO) with a nominal thickness of ≈70 nm grown by pulsed laser deposition at room temperature using a single ceramic target.…”
Section: Methodsmentioning
confidence: 99%
“…Increasing the thickness of the NiO layer by approximately a factor of three to 80 nm yielded an improved and rather constant leakage current for V G < 0 V, as has been reported for ZTO-based JFETs. [19] The field-effect mobility of each transistor has been estimated by calculating the transconductance g m from the transfer characteristics depicted in Figure 3a. Considering the channel resistance R S , the forward transconductance can be expressed by g m −1 = g max −1 + R S , where g max is the theoretical maximum of the transconductance, given by the channel conductivity.…”
Section: (4 Of 6)mentioning
confidence: 99%