Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Song, Taigon; Liu, Chang; Peng, Yarui; Lim, Sung Kyu

doi:10.1145/2463209.2488956

Cited by 33 publications

(22 citation statements)

References 3 publications

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“…The Fc in parameter was set to 0.5, which means that half of the tracks in the routing channel are connected to an LB input through a CB. We set the area of each TSV to 144µm 2 and calculate TSV capacitance using a compact multi-TSV coupling model [20] with FreePDK3D [21]. In this evaluation, we utilize the smallest delay of TSV is 47.80[ps] as a representative delay.…”

Section: Evaluation Conditionmentioning

confidence: 99%

Three Dimensional FPGA Architecture with Fewer TSVs

Amagasaki

Masato

Zhao

et al. 2018

IEICE Trans. Inf. & Syst.

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SUMMARYThree-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several facedown stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized. key words: three dimensional IC, 3D-FPGA, power estimation, facedown/face-up stacking

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Section: Evaluation Conditionmentioning

confidence: 99%

Three Dimensional FPGA Architecture with Fewer TSVs

Amagasaki

Masato

Zhao

et al. 2018

IEICE Trans. Inf. & Syst.

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show abstract

“…In this paper, on the basis of a result of the paper [2] and [3] for the purpose of applying the full-chip 3D IC design, we analyzed the impedance effect among the TSVs according to input frequency and analyzed impedance of the TSV-to-TSV in a multiple TSVto-TSVs in order to use as parameter of 3D IC design.…”

Section:   mentioning

confidence: 99%

The Impedance Analysis of Multiple TSV-to-TSV

Lee¹

2016

Journal of the Institute of Electronics and Information Enginee

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In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

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“…It can cause coupling noise and extra transmission delay and so on. The parasitic capacitance of TSV is a key point in its model [3]. In considering of the actual working environment of TSV, temperature cannot be ignored.…”

Section: Introductionmentioning

confidence: 99%

A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC

Deng¹,

Zhang²,

Li³

2015

Advances in Intelligent Systems Research

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Abstract. As the technology of three dimension integrated circuit (3D IC) develop quickly, through silicon via (TSV) plays a basic and important role.In consideration of real working environment, factors as temperature and working voltage are studied by TCAD simulator. And the contribution of physical sizes and the concentration of doping in the course are analyzed. A new analysis model of capacitance for TSV is given, which is with an error less than 4% with the measurement data. In the range of 25 to 125 degree centigrade with different physical sizes of TSV, this model of TSV's parasitic capacitance shows a better accuracy and takes less time than the former one. The neglect of temperature in course of design will lead to a big problem in real chip, an accurate mode considering temperature is important both in design and SI analysis.

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Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Cited by 33 publications

References 3 publications

Three Dimensional FPGA Architecture with Fewer TSVs

Three Dimensional FPGA Architecture with Fewer TSVs

The Impedance Analysis of Multiple TSV-to-TSV

A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC

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